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Remove the return_reg instruction.

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RISC architectures that take a return address in a register can use a
special-purpose `link` return value to do so.
This commit is contained in:
Jakob Stoklund Olesen
2017-04-19 16:08:16 -07:00
parent e44a5a4391
commit 0cb36c9031
6 changed files with 11 additions and 32 deletions
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11
lib/cretonne/meta/isa/riscv/encodings.py
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@@ -109,9 +109,8 @@ for inst, f3 in [
RV32.enc(inst.b1, SBzero, BRANCH(f3))
RV64.enc(inst.b1, SBzero, BRANCH(f3))
# Returns are a special case of JALR.
# Note: Return stack predictors will only recognize this as a return when the
# return address is provided in `x1`. We may want a special encoding to enforce
# that.
RV32.enc(base.return_reg.i32, Iret, JALR())
RV64.enc(base.return_reg.i64, Iret, JALR())
# Returns are a special case of JALR using %x1 to hold the return address.
# The return address is provided by a special-purpose `link` return value that
# is added by legalize_signature().
RV32.enc(base.x_return, Iret, JALR())
RV64.enc(base.x_return, Iret, JALR())