x64: Lower fcvt_from_uint in ISLE (#4684)
* Add a test for the existing behavior of fcvt_from_unit * Migrate the I8, I16, I32 cases of fcvt_from_uint * Implement the I64 case of fcvt_from_uint * Add a test for the existing behavior of fcvt_from_uint.f64x2 * Migrate fcvt_from_uint.f64x2 to ISLE * Lower the last case of `fcvt_from_uint` * Add a test for `fcvt_from_uint` * Finish lowering fcmp_from_uint * Format
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@@ -308,16 +308,6 @@ impl Inst {
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}
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}
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pub(crate) fn xmm_unary_rm_r_evex(op: Avx512Opcode, src: RegMem, dst: Writable<Reg>) -> Inst {
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src.assert_regclass_is(RegClass::Float);
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debug_assert!(dst.to_reg().class() == RegClass::Float);
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Inst::XmmUnaryRmREvex {
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op,
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src: XmmMem::new(src).unwrap(),
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dst: WritableXmm::from_writable_reg(dst).unwrap(),
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}
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}
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pub(crate) fn xmm_rm_r(op: SseOpcode, src: RegMem, dst: Writable<Reg>) -> Self {
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src.assert_regclass_is(RegClass::Float);
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debug_assert!(dst.to_reg().class() == RegClass::Float);
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@@ -418,27 +408,6 @@ impl Inst {
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Inst::XmmCmpRmR { op, src, dst }
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}
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pub(crate) fn cvt_u64_to_float_seq(
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dst_size: OperandSize,
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src: Writable<Reg>,
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tmp_gpr1: Writable<Reg>,
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tmp_gpr2: Writable<Reg>,
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dst: Writable<Reg>,
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) -> Inst {
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debug_assert!(dst_size.is_one_of(&[OperandSize::Size32, OperandSize::Size64]));
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debug_assert!(src.to_reg().class() == RegClass::Int);
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debug_assert!(tmp_gpr1.to_reg().class() == RegClass::Int);
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debug_assert!(tmp_gpr2.to_reg().class() == RegClass::Int);
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debug_assert!(dst.to_reg().class() == RegClass::Float);
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Inst::CvtUint64ToFloatSeq {
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src: WritableGpr::from_writable_reg(src).unwrap(),
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dst: WritableXmm::from_writable_reg(dst).unwrap(),
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tmp_gpr1: WritableGpr::from_writable_reg(tmp_gpr1).unwrap(),
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tmp_gpr2: WritableGpr::from_writable_reg(tmp_gpr2).unwrap(),
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dst_size,
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}
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}
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pub(crate) fn cvt_float_to_sint_seq(
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src_size: OperandSize,
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dst_size: OperandSize,
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