x64: Lower fcvt_from_uint in ISLE (#4684)

* Add a test for the existing behavior of fcvt_from_unit

* Migrate the I8, I16, I32 cases of fcvt_from_uint

* Implement the I64 case of fcvt_from_uint

* Add a test for the existing behavior of fcvt_from_uint.f64x2

* Migrate fcvt_from_uint.f64x2 to ISLE

* Lower the last case of `fcvt_from_uint`

* Add a test for `fcvt_from_uint`

* Finish lowering fcmp_from_uint

* Format
This commit is contained in:
Trevor Elliott
2022-08-11 12:28:41 -07:00
committed by GitHub
parent c4fd6a95da
commit 0c2e0494bd
8 changed files with 223 additions and 280 deletions

View File

@@ -308,16 +308,6 @@ impl Inst {
}
}
pub(crate) fn xmm_unary_rm_r_evex(op: Avx512Opcode, src: RegMem, dst: Writable<Reg>) -> Inst {
src.assert_regclass_is(RegClass::Float);
debug_assert!(dst.to_reg().class() == RegClass::Float);
Inst::XmmUnaryRmREvex {
op,
src: XmmMem::new(src).unwrap(),
dst: WritableXmm::from_writable_reg(dst).unwrap(),
}
}
pub(crate) fn xmm_rm_r(op: SseOpcode, src: RegMem, dst: Writable<Reg>) -> Self {
src.assert_regclass_is(RegClass::Float);
debug_assert!(dst.to_reg().class() == RegClass::Float);
@@ -418,27 +408,6 @@ impl Inst {
Inst::XmmCmpRmR { op, src, dst }
}
pub(crate) fn cvt_u64_to_float_seq(
dst_size: OperandSize,
src: Writable<Reg>,
tmp_gpr1: Writable<Reg>,
tmp_gpr2: Writable<Reg>,
dst: Writable<Reg>,
) -> Inst {
debug_assert!(dst_size.is_one_of(&[OperandSize::Size32, OperandSize::Size64]));
debug_assert!(src.to_reg().class() == RegClass::Int);
debug_assert!(tmp_gpr1.to_reg().class() == RegClass::Int);
debug_assert!(tmp_gpr2.to_reg().class() == RegClass::Int);
debug_assert!(dst.to_reg().class() == RegClass::Float);
Inst::CvtUint64ToFloatSeq {
src: WritableGpr::from_writable_reg(src).unwrap(),
dst: WritableXmm::from_writable_reg(dst).unwrap(),
tmp_gpr1: WritableGpr::from_writable_reg(tmp_gpr1).unwrap(),
tmp_gpr2: WritableGpr::from_writable_reg(tmp_gpr2).unwrap(),
dst_size,
}
}
pub(crate) fn cvt_float_to_sint_seq(
src_size: OperandSize,
dst_size: OperandSize,