x64: lower iabs.i64x2 using a single AVX512 instruction when possible (#2819)

* x64: add EVEX encoding mechanism

Also, includes an empty stub module for the VEX encoding.

* x64: lower abs.i64x2 to VPABSQ when available

* x64: refactor EVEX encodings to use `EvexInstruction`

This change replaces the `encode_evex` function with a builder-style struct, `EvexInstruction`. This approach clarifies the code, adds documentation, and results in slight speedups when benchmarked.

* x64: rename encoding CodeSink to ByteSink

cranelift/codegen/src/isa/x64/inst/args.rs

@@ -460,9 +460,7 @@ pub(crate) enum InstructionSet {
     BMI1,
     #[allow(dead_code)] // never constructed (yet).
     BMI2,
-    #[allow(dead_code)]
     AVX512F,
-    #[allow(dead_code)]
     AVX512VL,
 }
 
@@ -995,13 +993,11 @@ impl fmt::Display for SseOpcode {
 
 #[derive(Clone)]
 pub enum Avx512Opcode {
-    #[allow(dead_code)]
     Vpabsq,
 }
 
 impl Avx512Opcode {
     /// Which `InstructionSet`s support the opcode?
-    #[allow(dead_code)]
     pub(crate) fn available_from(&self) -> SmallVec<[InstructionSet; 2]> {
         match self {
             Avx512Opcode::Vpabsq => smallvec![InstructionSet::AVX512F, InstructionSet::AVX512VL],