T0b1/wasmtime
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Add Intel encodings for jump and branch instructions.

Browse Source 
Just implement jump, brz, and brnz as needed for WebAssembly.
This commit is contained in:
Jakob Stoklund Olesen
2017-07-18 14:54:34 -07:00
parent 2927878707
commit 0a7087732e
6 changed files with 188 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

22
filetests/isa/intel/binary32.cton
View File

@@ -262,6 +262,28 @@ ebb0:
; asm: call *%esi
call_indirect sig0, v2() ; bin: ff d6
; asm: testl %ecx, %ecx
; asm: je ebb1
brz v1, ebb1 ; bin: 85 c9 74 0e
; asm: testl %esi, %esi
; asm: je ebb1
brz v2, ebb1 ; bin: 85 f6 74 0a
; asm: testl %ecx, %ecx
; asm: jne ebb1
brnz v1, ebb1 ; bin: 85 c9 75 06
; asm: testl %esi, %esi
; asm: jne ebb1
brnz v2, ebb1 ; bin: 85 f6 75 02
; asm: jmp ebb2
jump ebb2 ; bin: eb 01
; asm: ebb1:
ebb1:
; asm: ret
return ; bin: c3
; asm: ebb2:
ebb2:
jump ebb1 ; bin: eb fd
}

56
filetests/isa/intel/binary64.cton
View File

@@ -192,7 +192,35 @@ ebb0:
; asm: tzcntq %rcx, %r10
[-,%r10] v208 = ctz v1 ; bin: f3 4c 0f bc d1
; asm: testq %rcx, %ecx
; asm: je ebb1
brz v1, ebb1 ; bin: 48 85 c9 74 1b
; asm: testq %rsi, %esi
; asm: je ebb1
brz v2, ebb1 ; bin: 48 85 f6 74 16
; asm: testq %r10, %r10d
; asm: je ebb1
brz v3, ebb1 ; bin: 4d 85 d2 74 11
; asm: testq %rcx, %ecx
; asm: jne ebb1
brnz v1, ebb1 ; bin: 48 85 c9 75 0c
; asm: test %rsi, %esi
; asm: jne ebb1
brnz v2, ebb1 ; bin: 48 85 f6 75 07
; asm: testq %r10, %r10d
; asm: jne ebb1
brnz v3, ebb1 ; bin: 4d 85 d2 75 02
; asm: jmp ebb2
jump ebb2 ; bin: eb 01
; asm: ebb1:
ebb1:
return ; bin: c3
; asm: ebb2:
ebb2:
jump ebb1 ; bin: eb fd
}
; Tests for i32 instructions in 64-bit mode.
@@ -384,5 +412,33 @@ ebb0:
; asm: tzcntl %ecx, %r10d
[-,%r10] v208 = ctz v1 ; bin: f3 44 0f bc d1
; asm: testl %ecx, %ecx
; asm: je ebb1
brz v1, ebb1 ; bin: 40 85 c9 74 1b
; asm: testl %esi, %esi
; asm: je ebb1
brz v2, ebb1 ; bin: 40 85 f6 74 16
; asm: testl %r10d, %r10d
; asm: je ebb1
brz v3, ebb1 ; bin: 45 85 d2 74 11
; asm: testl %ecx, %ecx
; asm: jne ebb1
brnz v1, ebb1 ; bin: 40 85 c9 75 0c
; asm: test %esi, %esi
; asm: jne ebb1
brnz v2, ebb1 ; bin: 40 85 f6 75 07
; asm: testl %r10d, %r10d
; asm: jne ebb1
brnz v3, ebb1 ; bin: 45 85 d2 75 02
; asm: jmp ebb2
jump ebb2 ; bin: eb 01
; asm: ebb1:
ebb1:
return ; bin: c3
; asm: ebb2:
ebb2:
jump ebb1 ; bin: eb fd
}

34
filetests/wasm/control.cton Normal file
View File

@@ -0,0 +1,34 @@
; Test basic code generation for control flow WebAssembly instructions.
test compile
set is_64bit=0
isa intel haswell
set is_64bit=1
isa intel haswell
function %br_if(i32) -> i32 {
ebb0(v0: i32):
v1 = iconst.i32 1
brz v0, ebb1(v1)
jump ebb2
ebb1(v2: i32):
return v2
ebb2:
jump ebb1(v0)
}
function %br_if_not(i32) -> i32 {
ebb0(v0: i32):
v1 = iconst.i32 1
brnz v0, ebb1(v0)
jump ebb2
ebb1(v2: i32):
return v2
ebb2:
jump ebb1(v0)
}