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Merge pull request #1954 from cfallin/b1649432

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AArch64: fix shift ops: mask shift amount.
This commit is contained in:
Chris Fallin
2020-07-01 09:33:29 -07:00
committed by GitHub
parent a351fa52b5 533f1c8d8b
commit 0a59a321bd
3 changed files with 18 additions and 2 deletions
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2
cranelift/codegen/src/isa/aarch64/lower.rs
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@@ -435,8 +435,10 @@ pub(crate) fn put_input_in_rs_immlogic<C: LowerCtx<I = Inst>>(
pub(crate) fn put_input_in_reg_immshift<C: LowerCtx<I = Inst>>( pub(crate) fn put_input_in_reg_immshift<C: LowerCtx<I = Inst>>(
ctx: &mut C, ctx: &mut C,
input: InsnInput, input: InsnInput,
shift_width_bits: usize,
) -> ResultRegImmShift { ) -> ResultRegImmShift {
if let Some(imm_value) = input_to_const(ctx, input) { if let Some(imm_value) = input_to_const(ctx, input) {
let imm_value = imm_value & ((shift_width_bits - 1) as u64);
if let Some(immshift) = ImmShift::maybe_from_u64(imm_value) { if let Some(immshift) = ImmShift::maybe_from_u64(imm_value) {
return ResultRegImmShift::ImmShift(immshift); return ResultRegImmShift::ImmShift(immshift);
} }

4
cranelift/codegen/src/isa/aarch64/lower_inst.rs
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@@ -460,7 +460,7 @@ pub(crate) fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
}; };
let rd = get_output_reg(ctx, outputs[0]); let rd = get_output_reg(ctx, outputs[0]);
let rn = put_input_in_reg(ctx, inputs[0], narrow_mode); let rn = put_input_in_reg(ctx, inputs[0], narrow_mode);
let rm = put_input_in_reg_immshift(ctx, inputs[1]); let rm = put_input_in_reg_immshift(ctx, inputs[1], ty_bits(ty));
let alu_op = match op { let alu_op = match op {
Opcode::Ishl => choose_32_64(ty, ALUOp::Lsl32, ALUOp::Lsl64), Opcode::Ishl => choose_32_64(ty, ALUOp::Lsl32, ALUOp::Lsl64),
Opcode::Ushr => choose_32_64(ty, ALUOp::Lsr32, ALUOp::Lsr64), Opcode::Ushr => choose_32_64(ty, ALUOp::Lsr32, ALUOp::Lsr64),
@@ -513,7 +513,7 @@ pub(crate) fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
NarrowValueMode::ZeroExtend64 NarrowValueMode::ZeroExtend64
}, },
); );
let rm = put_input_in_reg_immshift(ctx, inputs[1]); let rm = put_input_in_reg_immshift(ctx, inputs[1], ty_bits(ty));
if ty_bits_size == 32 || ty_bits_size == 64 { if ty_bits_size == 32 || ty_bits_size == 64 {
let alu_op = choose_32_64(ty, ALUOp::RotR32, ALUOp::RotR64); let alu_op = choose_32_64(ty, ALUOp::RotR32, ALUOp::RotR64);

14
cranelift/filetests/filetests/vcode/aarch64/shift-op.clif
View File

@@ -15,3 +15,17 @@ block0(v0: i64):
; nextln: mov sp, fp ; nextln: mov sp, fp
; nextln: ldp fp, lr, [sp], #16 ; nextln: ldp fp, lr, [sp], #16
; nextln: ret ; nextln: ret
function %f(i32) -> i32 {
block0(v0: i32):
v1 = iconst.i32 53
v2 = ishl.i32 v0, v1
return v2
}
; check: stp fp, lr, [sp, #-16]!
; nextln: mov fp, sp
; nextln: lsl w0, w0, #21
; nextln: mov sp, fp
; nextln: ldp fp, lr, [sp], #16
; nextln: ret