From 09a5b91b9dd42a96deb16448cc61b31cd2c288a6 Mon Sep 17 00:00:00 2001
From: Andrew Brown <andrew.brown@intel.com>
Date: Mon, 4 Jan 2021 16:09:28 -0800
Subject: [PATCH] x64: make several structures debuggable

---
 cranelift/codegen/src/isa/x64/inst/args.rs | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/cranelift/codegen/src/isa/x64/inst/args.rs b/cranelift/codegen/src/isa/x64/inst/args.rs
index 680d0921ff..898134644f 100644
--- a/cranelift/codegen/src/isa/x64/inst/args.rs
+++ b/cranelift/codegen/src/isa/x64/inst/args.rs
@@ -145,7 +145,7 @@ impl PrettyPrint for Amode {
 /// A Memory Address. These denote a 64-bit value only.
 /// Used for usual addressing modes as well as addressing modes used during compilation, when the
 /// moving SP offset is not known.
-#[derive(Clone)]
+#[derive(Clone, Debug)]
 pub enum SyntheticAmode {
     /// A real amode.
     Real(Amode),
@@ -286,7 +286,7 @@ impl PrettyPrintSized for RegMemImm {
 
 /// An operand which is either an integer Register or a value in Memory.  This can denote an 8, 16,
 /// 32, 64, or 128 bit value.
-#[derive(Clone)]
+#[derive(Clone, Debug)]
 pub enum RegMem {
     Reg { reg: Reg },
     Mem { addr: SyntheticAmode },