From 099b959d57f5b55d623bc489745b9e64370b6354 Mon Sep 17 00:00:00 2001
From: Pat Hickey <pat@moreproductive.org>
Date: Mon, 29 Jan 2018 13:38:26 -0800
Subject: [PATCH] TargetIsa implies a Display of shared and isa-specific flags

---
 lib/cretonne/src/isa/arm32/mod.rs | 7 +++++++
 lib/cretonne/src/isa/arm64/mod.rs | 7 +++++++
 lib/cretonne/src/isa/intel/mod.rs | 7 +++++++
 lib/cretonne/src/isa/mod.rs       | 6 ++++--
 lib/cretonne/src/isa/riscv/mod.rs | 7 +++++++
 5 files changed, 32 insertions(+), 2 deletions(-)

diff --git a/lib/cretonne/src/isa/arm32/mod.rs b/lib/cretonne/src/isa/arm32/mod.rs
index 49987f1e18..c3f295d4fb 100644
--- a/lib/cretonne/src/isa/arm32/mod.rs
+++ b/lib/cretonne/src/isa/arm32/mod.rs
@@ -13,6 +13,7 @@ use isa::Builder as IsaBuilder;
 use isa::{TargetIsa, RegInfo, RegClass, EncInfo};
 use ir;
 use regalloc;
+use std::fmt;
 
 #[allow(dead_code)]
 struct Isa {
@@ -108,3 +109,9 @@ impl TargetIsa for Isa {
         emit_function(func, binemit::emit_inst, sink)
     }
 }
+
+impl fmt::Display for Isa {
+    fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
+        write!(f, "{}\n{}", self.shared_flags, self.isa_flags)
+    }
+}
diff --git a/lib/cretonne/src/isa/arm64/mod.rs b/lib/cretonne/src/isa/arm64/mod.rs
index f8e7737c31..d0644ae2f6 100644
--- a/lib/cretonne/src/isa/arm64/mod.rs
+++ b/lib/cretonne/src/isa/arm64/mod.rs
@@ -13,6 +13,7 @@ use isa::Builder as IsaBuilder;
 use isa::{TargetIsa, RegInfo, RegClass, EncInfo};
 use ir;
 use regalloc;
+use std::fmt;
 
 #[allow(dead_code)]
 struct Isa {
@@ -101,3 +102,9 @@ impl TargetIsa for Isa {
         emit_function(func, binemit::emit_inst, sink)
     }
 }
+
+impl fmt::Display for Isa {
+    fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
+        write!(f, "{}\n{}", self.shared_flags, self.isa_flags)
+    }
+}
diff --git a/lib/cretonne/src/isa/intel/mod.rs b/lib/cretonne/src/isa/intel/mod.rs
index 3123e7f0cb..3f02890a82 100644
--- a/lib/cretonne/src/isa/intel/mod.rs
+++ b/lib/cretonne/src/isa/intel/mod.rs
@@ -15,6 +15,7 @@ use ir;
 use regalloc;
 use result;
 use timing;
+use std::fmt;
 
 
 #[allow(dead_code)]
@@ -116,3 +117,9 @@ impl TargetIsa for Isa {
         abi::prologue_epilogue(func, self)
     }
 }
+
+impl fmt::Display for Isa {
+    fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
+        write!(f, "{}\n{}", self.shared_flags, self.isa_flags)
+    }
+}
diff --git a/lib/cretonne/src/isa/mod.rs b/lib/cretonne/src/isa/mod.rs
index 1fdaa79f09..b4227d2550 100644
--- a/lib/cretonne/src/isa/mod.rs
+++ b/lib/cretonne/src/isa/mod.rs
@@ -53,6 +53,7 @@ use regalloc;
 use result;
 use timing;
 use isa::enc_tables::Encodings;
+use std::fmt;
 
 #[cfg(build_riscv)]
 pub mod riscv;
@@ -146,8 +147,9 @@ pub type Legalize = fn(ir::Inst,
                        &mut flowgraph::ControlFlowGraph)
                        -> bool;
 
-/// Methods that are specialized to a target ISA.
-pub trait TargetIsa {
+/// Methods that are specialized to a target ISA. Implies a Display trait that shows the
+/// shared flags, as well as any isa-specific flags.
+pub trait TargetIsa: fmt::Display {
     /// Get the name of this ISA.
     fn name(&self) -> &'static str;
 
diff --git a/lib/cretonne/src/isa/riscv/mod.rs b/lib/cretonne/src/isa/riscv/mod.rs
index 790a788a24..2fd0d5cdb9 100644
--- a/lib/cretonne/src/isa/riscv/mod.rs
+++ b/lib/cretonne/src/isa/riscv/mod.rs
@@ -13,6 +13,7 @@ use isa::Builder as IsaBuilder;
 use isa::{TargetIsa, RegInfo, RegClass, EncInfo};
 use ir;
 use regalloc;
+use std::fmt;
 
 #[allow(dead_code)]
 struct Isa {
@@ -252,3 +253,9 @@ mod tests {
         assert_eq!(encstr(&*isa, isa.encode(&dfg, &mul32, types::I32)), "R#10c");
     }
 }
+
+impl fmt::Display for Isa {
+    fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
+        write!(f, "{}\n{}", self.shared_flags, self.isa_flags)
+    }
+}