Cranelift AArch64: Add initial support for the Armv8.1 atomics

This commit enables Cranelift's AArch64 backend to generate code
for instruction set extensions (previously only the base Armv8-A
architecture was supported); also, it makes it possible to detect
the extensions supported by the host when JIT compiling. The new
functionality is applied to the IR instruction `AtomicCas`.

Copyright (c) 2021, Arm Limited.

cranelift/native/src/lib.rs

@@ -105,6 +105,20 @@ pub fn builder_with_options(
         }
     }
 
+    // `stdsimd` is necessary for std::is_aarch64_feature_detected!().
+    #[cfg(all(target_arch = "aarch64", feature = "stdsimd"))]
+    {
+        use cranelift_codegen::settings::Configurable;
+
+        if !infer_native_flags {
+            return Ok(isa_builder);
+        }
+
+        if std::is_aarch64_feature_detected!("lse") {
+            isa_builder.enable("has_lse").unwrap();
+        }
+    }
+
     // squelch warnings about unused mut/variables on some platforms.
     drop(&mut isa_builder);
     drop(infer_native_flags);