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Expand x86 registers to include 32 XMM registers

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The EVEX encoding format (e.g. in AVX-512) allows addressing 32 registers instead of 16. The FPR register class currently defines 16 registers, `%xmm0`-`%xmm15`; that class is kept as-is with this change. A larger class, FPR32, is added as a super-class of FPR using a larger bank of registers, `%xmm0`-`%xmm31`.
This commit is contained in:
Andrew Brown
2020-02-14 13:24:13 -08:00
parent 1d15054310
commit 079fcafcb1
2 changed files with 56 additions and 32 deletions
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15
cranelift/codegen/meta/src/isa/x86/registers.rs
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@@ -3,6 +3,11 @@ use crate::cdsl::regs::{IsaRegs, IsaRegsBuilder, RegBankBuilder, RegClassBuilder
pub(crate) fn define() -> IsaRegs {
let mut regs = IsaRegsBuilder::new();
let builder = RegBankBuilder::new("FloatRegs", "xmm")
.units(32)
.track_pressure(true);
let float_regs = regs.add_bank(builder);
let builder = RegBankBuilder::new("IntRegs", "r")
.units(16)
.names(vec!["rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi"])
@@ -10,11 +15,6 @@ pub(crate) fn define() -> IsaRegs {
.pinned_reg(15);
let int_regs = regs.add_bank(builder);
let builder = RegBankBuilder::new("FloatRegs", "xmm")
.units(16)
.track_pressure(true);
let float_regs = regs.add_bank(builder);
let builder = RegBankBuilder::new("FlagRegs", "")
.units(1)
.names(vec!["rflags"])
@@ -24,7 +24,10 @@ pub(crate) fn define() -> IsaRegs {
let builder = RegClassBuilder::new_toplevel("GPR", int_regs);
let gpr = regs.add_class(builder);
let builder = RegClassBuilder::new_toplevel("FPR", float_regs);
let builder = RegClassBuilder::new_toplevel("FPR32", float_regs);
let fpr32 = regs.add_class(builder);
let builder = RegClassBuilder::subclass_of("FPR", fpr32, 0, 16);
let fpr = regs.add_class(builder);
let builder = RegClassBuilder::new_toplevel("FLAG", flag_reg);