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aarch64: correctly display fpu loads and stores;

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This commit is contained in:
Benjamin Bouvier
2020-04-23 19:23:05 +02:00
parent d166cff283
commit 077556ac17
1 changed files with 18 additions and 12 deletions
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30
cranelift/codegen/src/isa/aarch64/inst/mod.rs
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@@ -2297,35 +2297,41 @@ impl ShowWithRRU for Inst {
} }
&Inst::FpuLoad32 { rd, ref mem, .. } => { &Inst::FpuLoad32 { rd, ref mem, .. } => {
let rd = show_freg_sized(rd.to_reg(), mb_rru, InstSize::Size32); let rd = show_freg_sized(rd.to_reg(), mb_rru, InstSize::Size32);
let mem = mem.show_rru_sized(mb_rru, /* size = */ 4); let (mem_str, mem) = mem_finalize_for_show(mem, mb_rru);
format!("ldr {}, {}", rd, mem) let mem = mem.show_rru(mb_rru);
format!("{}ldr {}, {}", mem_str, rd, mem)
} }
&Inst::FpuLoad64 { rd, ref mem, .. } => { &Inst::FpuLoad64 { rd, ref mem, .. } => {
let rd = show_freg_sized(rd.to_reg(), mb_rru, InstSize::Size64); let rd = show_freg_sized(rd.to_reg(), mb_rru, InstSize::Size64);
let mem = mem.show_rru_sized(mb_rru, /* size = */ 8); let (mem_str, mem) = mem_finalize_for_show(mem, mb_rru);
format!("ldr {}, {}", rd, mem) let mem = mem.show_rru(mb_rru);
format!("{}ldr {}, {}", mem_str, rd, mem)
} }
&Inst::FpuLoad128 { rd, ref mem, .. } => { &Inst::FpuLoad128 { rd, ref mem, .. } => {
let rd = rd.to_reg().show_rru(mb_rru); let rd = rd.to_reg().show_rru(mb_rru);
let rd = "q".to_string() + &rd[1..]; let rd = "q".to_string() + &rd[1..];
let mem = mem.show_rru_sized(mb_rru, /* size = */ 8); let (mem_str, mem) = mem_finalize_for_show(mem, mb_rru);
format!("ldr {}, {}", rd, mem) let mem = mem.show_rru(mb_rru);
format!("{}ldr {}, {}", mem_str, rd, mem)
} }
&Inst::FpuStore32 { rd, ref mem, .. } => { &Inst::FpuStore32 { rd, ref mem, .. } => {
let rd = show_freg_sized(rd, mb_rru, InstSize::Size32); let rd = show_freg_sized(rd, mb_rru, InstSize::Size32);
let mem = mem.show_rru_sized(mb_rru, /* size = */ 4); let (mem_str, mem) = mem_finalize_for_show(mem, mb_rru);
format!("str {}, {}", rd, mem) let mem = mem.show_rru(mb_rru);
format!("{}str {}, {}", mem_str, rd, mem)
} }
&Inst::FpuStore64 { rd, ref mem, .. } => { &Inst::FpuStore64 { rd, ref mem, .. } => {
let rd = show_freg_sized(rd, mb_rru, InstSize::Size64); let rd = show_freg_sized(rd, mb_rru, InstSize::Size64);
let mem = mem.show_rru_sized(mb_rru, /* size = */ 8); let (mem_str, mem) = mem_finalize_for_show(mem, mb_rru);
format!("str {}, {}", rd, mem) let mem = mem.show_rru(mb_rru);
format!("{}str {}, {}", mem_str, rd, mem)
} }
&Inst::FpuStore128 { rd, ref mem, .. } => { &Inst::FpuStore128 { rd, ref mem, .. } => {
let rd = rd.show_rru(mb_rru); let rd = rd.show_rru(mb_rru);
let rd = "q".to_string() + &rd[1..]; let rd = "q".to_string() + &rd[1..];
let mem = mem.show_rru_sized(mb_rru, /* size = */ 8); let (mem_str, mem) = mem_finalize_for_show(mem, mb_rru);
format!("str {}, {}", rd, mem) let mem = mem.show_rru(mb_rru);
format!("{}str {}, {}", mem_str, rd, mem)
} }
&Inst::LoadFpuConst32 { rd, const_data } => { &Inst::LoadFpuConst32 { rd, const_data } => {
let rd = show_freg_sized(rd.to_reg(), mb_rru, InstSize::Size32); let rd = show_freg_sized(rd.to_reg(), mb_rru, InstSize::Size32);