diff --git a/cranelift/codegen/src/isa/riscv64/inst.isle b/cranelift/codegen/src/isa/riscv64/inst.isle
index dc30e1e924..4e43edc8de 100644
--- a/cranelift/codegen/src/isa/riscv64/inst.isle
+++ b/cranelift/codegen/src/isa/riscv64/inst.isle
@@ -944,7 +944,7 @@
 
       ;; add low and high together.
       (result Reg (alu_add low high)))
-    (value_regs result (zero_reg))))
+    (value_regs result (load_u64_constant 0))))
 
 (convert u8 i32 u8_as_i32)
 (decl u8_as_i32 (u8) i32)
@@ -999,7 +999,7 @@
       (low Reg (gen_select_reg (IntCC.Equal) constant_64 high low_part (zero_reg)))
       ;; add low and high together.
       (result Reg (alu_add high low)))
-    (value_regs result (zero_reg))))
+    (value_regs result (load_u64_constant 0))))
 
 (decl gen_extend (Reg bool u8 u8) Reg)
 (rule
@@ -1035,11 +1035,11 @@
 ;;;; for I128 unsigned extend.
 (rule 1
   (lower_extend r $false 64 128)
-  (value_regs (gen_move2 r $I64 $I64) (zero_reg)))
+  (value_regs (gen_move2 r $I64 $I64) (load_u64_constant 0)))
 
 (rule
   (lower_extend r $false from_bits 128)
-  (value_regs (gen_extend r $false from_bits 64) (zero_reg)))
+  (value_regs (gen_extend r $false from_bits 64) (load_u64_constant 0)))
 
 ;; extract the sign bit of integer.
 (decl ext_sign_bit (Type Reg) Reg)
@@ -1223,7 +1223,7 @@
       (high Reg (lower_popcnt (value_regs_get a 1) $I64))
       ;; add toghter.
       (result Reg (alu_add low high)))
-    (value_regs result (zero_reg))))
+    (value_regs result (load_u64_constant 0))))
 
 (decl lower_i128_rotl (ValueRegs ValueRegs) ValueRegs)
 (rule
@@ -1378,7 +1378,7 @@
       (tmp  ValueRegs (lower_clz_i128 (value_regs low high)))
       (count Reg (value_regs_get tmp 0))
       (result Reg (alu_rr_imm12 (AluOPRRI.Addi) count (imm12_const -1))))
-    (value_regs result (zero_reg))))
+    (value_regs result (load_u64_constant 0))))
 
 (decl imm12_const (i32) Imm12)
 (extern constructor imm12_const imm12_const)
diff --git a/cranelift/codegen/src/isa/riscv64/lower.isle b/cranelift/codegen/src/isa/riscv64/lower.isle
index 754d03961f..ce29982de0 100644
--- a/cranelift/codegen/src/isa/riscv64/lower.isle
+++ b/cranelift/codegen/src/isa/riscv64/lower.isle
@@ -642,8 +642,7 @@
 (rule 1
   (lower (has_type $I128 (bint (valueregs_2_reg x))))
   (let ((tmp Reg (gen_bint x)))
-   (value_regs tmp (zero_reg))) 
-)
+   (value_regs tmp (load_u64_constant 0))))
 
 ;;;;;  Rules for `isplit`;;;;;;;;;
 (rule 
diff --git a/cranelift/filetests/filetests/isa/riscv64/bitops.clif b/cranelift/filetests/filetests/isa/riscv64/bitops.clif
index 7bf1300935..59ec0be9c3 100644
--- a/cranelift/filetests/filetests/isa/riscv64/bitops.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/bitops.clif
@@ -120,7 +120,7 @@ block0(v0: i128):
 ;   li t0,64
 ;   select_reg t2,t3,zero##condition=(t0 eq a4)
 ;   add a0,a4,t2
-;   mv a1,zero
+;   li a1,0
 ;   ret
 
 function %c(i8) -> i8 {
@@ -194,8 +194,9 @@ block0(v0: i128):
 ;   li a5,64
 ;   select_reg a7,a3,zero##condition=(a5 eq t2)
 ;   add t4,t2,a7
+;   li t1,0
 ;   addi a0,t4,-1
-;   mv a1,zero
+;   li a1,0
 ;   ret
 
 function %d(i8) -> i8 {
@@ -254,7 +255,7 @@ block0(v0: i128):
 ;   li t0,64
 ;   select_reg t2,t3,zero##condition=(t0 eq a4)
 ;   add a0,a4,t2
-;   mv a1,zero
+;   li a1,0
 ;   ret
 
 function %d(i128) -> i128 {
@@ -267,7 +268,7 @@ block0(v0: i128):
 ;   popcnt a4,a0##ty=i64 tmp=a2 step=a3
 ;   popcnt t3,a1##ty=i64 tmp=a6 step=a7
 ;   add a0,a4,t3
-;   mv a1,zero
+;   li a1,0
 ;   ret
 
 function %d(i64) -> i64 {
diff --git a/cranelift/filetests/filetests/isa/riscv64/extend-op.clif b/cranelift/filetests/filetests/isa/riscv64/extend-op.clif
index 26588ad12a..0839176dcf 100644
--- a/cranelift/filetests/filetests/isa/riscv64/extend-op.clif
+++ b/cranelift/filetests/filetests/isa/riscv64/extend-op.clif
@@ -34,7 +34,7 @@ block0(v0: i64):
 }
 
 ; block0:
-;   mv a1,zero
+;   li a1,0
 ;   ret
 
 function %i128_sextend_i64(i64) -> i128 {
@@ -56,7 +56,7 @@ block0(v0: i32):
 
 ; block0:
 ;   uext.w a0,a0
-;   mv a1,zero
+;   li a1,0
 ;   ret
 
 function %i128_sextend_i32(i32) -> i128 {
@@ -79,7 +79,7 @@ block0(v0: i16):
 
 ; block0:
 ;   uext.h a0,a0
-;   mv a1,zero
+;   li a1,0
 ;   ret
 
 function %i128_sextend_i16(i16) -> i128 {
@@ -102,7 +102,7 @@ block0(v0: i8):
 
 ; block0:
 ;   uext.b a0,a0
-;   mv a1,zero
+;   li a1,0
 ;   ret
 
 function %i128_sextend_i8(i8) -> i128 {
diff --git a/cranelift/filetests/filetests/runtests/riscv64_issue_4996.clif b/cranelift/filetests/filetests/runtests/riscv64_issue_4996.clif
new file mode 100644
index 0000000000..f019b90261
--- /dev/null
+++ b/cranelift/filetests/filetests/runtests/riscv64_issue_4996.clif
@@ -0,0 +1,24 @@
+test interpret
+test run
+set enable_llvm_abi_extensions=true
+target riscv64
+
+; This is a regression test for https://github.com/bytecodealliance/wasmtime/issues/4996.
+function %issue4996() -> i128, i64 system_v {
+    block0:
+        v5 = bconst.b1 false
+        brz v5, block3  ; v5 = false
+        jump block1
+    block1:
+        v12 = iconst.i64 0
+        v13 = uextend.i128 v12  ; v12 = 0
+        jump block5(v13)
+
+    block3:
+        v21 = iconst.i128 0
+        jump block5(v21)  ; v21 = 0
+    block5(v23: i128):
+        v29 = iconst.i64 0
+        return v23, v29  ; v29 = 0
+}
+; run: %issue4996() == [0,0]
\ No newline at end of file