Remove the Cranelift vselect instruction (#5918)

* Remove the Cranelift `vselect` instruction

This instruction is documented as selecting lanes based on the "truthy"
value of the condition lane, but the current status of the
implementation of this instruction is:

* x64 - uses the high bit for `f32x4` and `f64x2` and otherwise uses the
  high bit of each byte doing a byte-wise lane select rather than
  whatever the controlling type is.

* AArch64 - this is the same as `bitselect` which is a bit-wise
  selection rather than a lane-wise selection.

* s390x - this is the same as AArch64, a bit-wise selection rather than
  lane-wise.

* interpreter - the interpreter implements the documented semantics of
  selecting based on "truthy" values.

Coupled with the status of the implementation is the fact that this
instruction is not used by WebAssembly SIMD today either. The only use
of this instruction in Cranelift is the nan-canonicalization pass. By
moving nan-canonicalization to `bitselect`, since that has the desired
semantics, there's no longer any need for `vselect`.

Given this situation this commit subsqeuently removes `vselect` and all
usage of it throughout Cranelift.

Closes #5917

* Review comments

* Bring back vselect opts as bitselect opts

* Clean up vselect usage in the interpreter

* Move bitcast in nan canonicalization

* Add a comment about float optimization

cranelift/filetests/filetests/egraph/bitselect.clif

@@ -5,10 +5,10 @@ target x86_64
 target aarch64
 target s390x
 
-function %vselect_sgt_to_smax(i32x4, i32x4) -> i32x4 {
+function %bitselect_sgt_to_smax(i32x4, i32x4) -> i32x4 {
 block0(v0: i32x4, v1: i32x4):
     v2 = icmp sgt v0, v1
-    v3 = vselect v2, v0, v1
+    v3 = bitselect v2, v0, v1
     return v3
 }
 
@@ -17,11 +17,11 @@ block0(v0: i32x4, v1: i32x4):
 ; check:    return v4
 
 
-; This tests an inverted vselect, where the operands are swapped.
-function %vselect_sgt_to_smax(i32x4, i32x4) -> i32x4 {
+; This tests an inverted bitselect, where the operands are swapped.
+function %bitselect_sgt_to_smax(i32x4, i32x4) -> i32x4 {
 block0(v0: i32x4, v1: i32x4):
     v2 = icmp sgt v0, v1
-    v3 = vselect v2, v1, v0
+    v3 = bitselect v2, v1, v0
     return v3
 }
 
@@ -31,10 +31,10 @@ block0(v0: i32x4, v1: i32x4):
 
 
 
-function %vselect_sge_to_smax(i32x4, i32x4) -> i32x4 {
+function %bitselect_sge_to_smax(i32x4, i32x4) -> i32x4 {
 block0(v0: i32x4, v1: i32x4):
     v2 = icmp sge v0, v1
-    v3 = vselect v2, v0, v1
+    v3 = bitselect v2, v0, v1
     return v3
 }
 
@@ -43,10 +43,10 @@ block0(v0: i32x4, v1: i32x4):
 ; check:    return v4
 
 
-function %vselect_ugt_to_umax(i32x4, i32x4) -> i32x4 {
+function %bitselect_ugt_to_umax(i32x4, i32x4) -> i32x4 {
 block0(v0: i32x4, v1: i32x4):
     v2 = icmp ugt v0, v1
-    v3 = vselect v2, v0, v1
+    v3 = bitselect v2, v0, v1
     return v3
 }
 
@@ -55,10 +55,10 @@ block0(v0: i32x4, v1: i32x4):
 ; check:    return v4
 
 
-function %vselect_uge_to_umax(i32x4, i32x4) -> i32x4 {
+function %bitselect_uge_to_umax(i32x4, i32x4) -> i32x4 {
 block0(v0: i32x4, v1: i32x4):
     v2 = icmp uge v0, v1
-    v3 = vselect v2, v0, v1
+    v3 = bitselect v2, v0, v1
     return v3
 }
 
@@ -68,10 +68,10 @@ block0(v0: i32x4, v1: i32x4):
 
 
 
-function %vselect_slt_to_smin(i32x4, i32x4) -> i32x4 {
+function %bitselect_slt_to_smin(i32x4, i32x4) -> i32x4 {
 block0(v0: i32x4, v1: i32x4):
     v2 = icmp slt v0, v1
-    v3 = vselect v2, v0, v1
+    v3 = bitselect v2, v0, v1
     return v3
 }
 
@@ -80,10 +80,10 @@ block0(v0: i32x4, v1: i32x4):
 ; check:    return v4
 
 
-function %vselect_sle_to_smin(i32x4, i32x4) -> i32x4 {
+function %bitselect_sle_to_smin(i32x4, i32x4) -> i32x4 {
 block0(v0: i32x4, v1: i32x4):
     v2 = icmp sle v0, v1
-    v3 = vselect v2, v0, v1
+    v3 = bitselect v2, v0, v1
     return v3
 }
 
@@ -92,10 +92,10 @@ block0(v0: i32x4, v1: i32x4):
 ; check:    return v4
 
 
-function %vselect_ult_to_umin(i32x4, i32x4) -> i32x4 {
+function %bitselect_ult_to_umin(i32x4, i32x4) -> i32x4 {
 block0(v0: i32x4, v1: i32x4):
     v2 = icmp ult v0, v1
-    v3 = vselect v2, v0, v1
+    v3 = bitselect v2, v0, v1
     return v3
 }
 
@@ -104,10 +104,10 @@ block0(v0: i32x4, v1: i32x4):
 ; check:    return v4
 
 
-function %vselect_ule_to_umin(i32x4, i32x4) -> i32x4 {
+function %bitselect_ule_to_umin(i32x4, i32x4) -> i32x4 {
 block0(v0: i32x4, v1: i32x4):
     v2 = icmp ule v0, v1
-    v3 = vselect v2, v0, v1
+    v3 = bitselect v2, v0, v1
     return v3
 }
 
@@ -117,38 +117,14 @@ block0(v0: i32x4, v1: i32x4):
 
 
 
-function %vselect_with_different_regs_does_not_optimize(i32x4, i32x4, i32x4, i32x4) -> i32x4 {
+function %bitselect_with_different_regs_does_not_optimize(i32x4, i32x4, i32x4, i32x4) -> i32x4 {
 block0(v0: i32x4, v1: i32x4, v2: i32x4, v3: i32x4):
     v4 = icmp ule v0, v1
-    v5 = vselect v4, v2, v3
+    v5 = bitselect v4, v2, v3
     return v5
 }
 
 ; check: block0(v0: i32x4, v1: i32x4, v2: i32x4, v3: i32x4):
 ; check:    v4 = icmp ule v0, v1
-; check:    v5 = vselect v4, v2, v3
+; check:    v5 = bitselect v4, v2, v3
 ; check:    return v5
-
-
-
-function %vselect_fcmp_gt_to_fmax_pseudo(f32x4, f32x4) -> f32x4 {
-block0(v0: f32x4, v1: f32x4):
-    v2 = fcmp gt v0, v1
-    v3 = vselect v2, v0, v1
-    return v3
-}
-
-; check: block0(v0: f32x4, v1: f32x4):
-; check:    v4 = fmax_pseudo v0, v1
-; check:    return v4
-
-function %vselect_fcmp_lt_to_fmin_pseudo(f32x4, f32x4) -> f32x4 {
-block0(v0: f32x4, v1: f32x4):
-    v2 = fcmp lt v0, v1
-    v3 = vselect v2, v0, v1
-    return v3
-}
-
-; check: block0(v0: f32x4, v1: f32x4):
-; check:    v4 = fmin_pseudo v0, v1
-; check:    return v4