x64 and aarch64: carry MemFlags on loads/stores; don't emit trap info unless an op can trap.
This end result was previously enacted by carrying a `SourceLoc` on every load/store, which was somewhat cumbersome, and only indirectly encoded metadata about a memory reference (can it trap) by its presence or absence. We have a type for this -- `MemFlags` -- that tells us everything we might want to know about a load or store, and we should plumb it through to code emission instead. This PR attaches a `MemFlags` to an `Amode` on x64, and puts it on load and store `Inst` variants on aarch64. These two choices seem to factor things out in the nicest way: there are relatively few load/store insts on aarch64 but many addressing modes, while the opposite is true on x64.
This commit is contained in:
Chris Fallin
@@ -9,7 +9,7 @@ use crate::ir::types::{
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F64X2, FFLAGS, I16, I16X4, I16X8, I32, I32X2, I32X4, I64, I64X2, I8, I8X16, I8X8, IFLAGS, R32,
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R64,
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};
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use crate::ir::{ExternalName, Opcode, SourceLoc, TrapCode, Type};
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use crate::ir::{ExternalName, MemFlags, Opcode, SourceLoc, TrapCode, Type};
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use crate::isa::CallConv;
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use crate::machinst::*;
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use crate::{settings, CodegenError, CodegenResult};
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@@ -523,57 +523,68 @@ pub enum Inst {
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ULoad8 {
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rd: Writable<Reg>,
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mem: AMode,
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flags: MemFlags,
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},
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/// A signed (sign-extending) 8-bit load.
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SLoad8 {
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rd: Writable<Reg>,
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mem: AMode,
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flags: MemFlags,
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},
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/// An unsigned (zero-extending) 16-bit load.
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ULoad16 {
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rd: Writable<Reg>,
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mem: AMode,
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flags: MemFlags,
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},
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/// A signed (sign-extending) 16-bit load.
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SLoad16 {
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rd: Writable<Reg>,
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mem: AMode,
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flags: MemFlags,
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},
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/// An unsigned (zero-extending) 32-bit load.
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ULoad32 {
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rd: Writable<Reg>,
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mem: AMode,
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flags: MemFlags,
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},
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/// A signed (sign-extending) 32-bit load.
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SLoad32 {
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rd: Writable<Reg>,
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mem: AMode,
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flags: MemFlags,
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},
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/// A 64-bit load.
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ULoad64 {
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rd: Writable<Reg>,
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mem: AMode,
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flags: MemFlags,
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},
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/// An 8-bit store.
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Store8 {
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rd: Reg,
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mem: AMode,
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flags: MemFlags,
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},
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/// A 16-bit store.
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Store16 {
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rd: Reg,
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mem: AMode,
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flags: MemFlags,
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},
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/// A 32-bit store.
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Store32 {
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rd: Reg,
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mem: AMode,
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flags: MemFlags,
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},
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/// A 64-bit store.
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Store64 {
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rd: Reg,
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mem: AMode,
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flags: MemFlags,
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},
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/// A store of a pair of registers.
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@@ -581,12 +592,14 @@ pub enum Inst {
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rt: Reg,
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rt2: Reg,
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mem: PairAMode,
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flags: MemFlags,
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},
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/// A load of a pair of registers.
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LoadP64 {
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rt: Writable<Reg>,
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rt2: Writable<Reg>,
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mem: PairAMode,
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flags: MemFlags,
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},
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/// A MOV instruction. These are encoded as ORR's (AluRRR form) but we
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@@ -782,31 +795,37 @@ pub enum Inst {
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FpuLoad32 {
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rd: Writable<Reg>,
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mem: AMode,
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flags: MemFlags,
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},
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/// Floating-point store, single-precision (32 bit).
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FpuStore32 {
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rd: Reg,
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mem: AMode,
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flags: MemFlags,
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},
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/// Floating-point load, double-precision (64 bit).
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FpuLoad64 {
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rd: Writable<Reg>,
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mem: AMode,
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flags: MemFlags,
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},
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/// Floating-point store, double-precision (64 bit).
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FpuStore64 {
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rd: Reg,
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mem: AMode,
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flags: MemFlags,
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},
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/// Floating-point/vector load, 128 bit.
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FpuLoad128 {
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rd: Writable<Reg>,
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mem: AMode,
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flags: MemFlags,
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},
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/// Floating-point/vector store, 128 bit.
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FpuStore128 {
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rd: Reg,
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mem: AMode,
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flags: MemFlags,
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},
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LoadFpuConst64 {
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@@ -1411,24 +1430,48 @@ impl Inst {
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}
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/// Generic constructor for a load (zero-extending where appropriate).
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pub fn gen_load(into_reg: Writable<Reg>, mem: AMode, ty: Type) -> Inst {
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pub fn gen_load(into_reg: Writable<Reg>, mem: AMode, ty: Type, flags: MemFlags) -> Inst {
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match ty {
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B1 | B8 | I8 => Inst::ULoad8 { rd: into_reg, mem },
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B16 | I16 => Inst::ULoad16 { rd: into_reg, mem },
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B32 | I32 | R32 => Inst::ULoad32 { rd: into_reg, mem },
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B64 | I64 | R64 => Inst::ULoad64 { rd: into_reg, mem },
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F32 => Inst::FpuLoad32 { rd: into_reg, mem },
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F64 => Inst::FpuLoad64 { rd: into_reg, mem },
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B1 | B8 | I8 => Inst::ULoad8 {
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rd: into_reg,
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mem,
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flags,
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},
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B16 | I16 => Inst::ULoad16 {
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rd: into_reg,
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mem,
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flags,
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},
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B32 | I32 | R32 => Inst::ULoad32 {
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rd: into_reg,
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mem,
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flags,
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},
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B64 | I64 | R64 => Inst::ULoad64 {
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rd: into_reg,
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mem,
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flags,
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},
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F32 => Inst::FpuLoad32 {
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rd: into_reg,
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mem,
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flags,
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},
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F64 => Inst::FpuLoad64 {
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rd: into_reg,
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mem,
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flags,
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},
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_ => {
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if ty.is_vector() {
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let bits = ty_bits(ty);
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let rd = into_reg;
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if bits == 128 {
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Inst::FpuLoad128 { rd, mem }
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Inst::FpuLoad128 { rd, mem, flags }
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} else {
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assert_eq!(bits, 64);
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Inst::FpuLoad64 { rd, mem }
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Inst::FpuLoad64 { rd, mem, flags }
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}
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} else {
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unimplemented!("gen_load({})", ty);
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@@ -1438,24 +1481,48 @@ impl Inst {
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}
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/// Generic constructor for a store.
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pub fn gen_store(mem: AMode, from_reg: Reg, ty: Type) -> Inst {
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pub fn gen_store(mem: AMode, from_reg: Reg, ty: Type, flags: MemFlags) -> Inst {
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match ty {
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B1 | B8 | I8 => Inst::Store8 { rd: from_reg, mem },
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B16 | I16 => Inst::Store16 { rd: from_reg, mem },
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B32 | I32 | R32 => Inst::Store32 { rd: from_reg, mem },
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B64 | I64 | R64 => Inst::Store64 { rd: from_reg, mem },
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F32 => Inst::FpuStore32 { rd: from_reg, mem },
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F64 => Inst::FpuStore64 { rd: from_reg, mem },
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B1 | B8 | I8 => Inst::Store8 {
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rd: from_reg,
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mem,
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flags,
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},
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B16 | I16 => Inst::Store16 {
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rd: from_reg,
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mem,
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flags,
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},
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B32 | I32 | R32 => Inst::Store32 {
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rd: from_reg,
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mem,
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flags,
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},
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B64 | I64 | R64 => Inst::Store64 {
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rd: from_reg,
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mem,
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flags,
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},
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F32 => Inst::FpuStore32 {
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rd: from_reg,
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mem,
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flags,
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},
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F64 => Inst::FpuStore64 {
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rd: from_reg,
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mem,
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flags,
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},
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_ => {
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if ty.is_vector() {
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let bits = ty_bits(ty);
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let rd = from_reg;
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if bits == 128 {
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Inst::FpuStore128 { rd, mem }
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Inst::FpuStore128 { rd, mem, flags }
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} else {
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assert_eq!(bits, 64);
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Inst::FpuStore64 { rd, mem }
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Inst::FpuStore64 { rd, mem, flags }
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}
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} else {
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unimplemented!("gen_store({})", ty);
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@@ -2126,6 +2193,7 @@ fn aarch64_map_regs<RUM: RegUsageMapper>(inst: &mut Inst, mapper: &RUM) {
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ref mut rt,
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ref mut rt2,
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ref mut mem,
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..
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} => {
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map_use(mapper, rt);
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map_use(mapper, rt2);
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@@ -2135,6 +2203,7 @@ fn aarch64_map_regs<RUM: RegUsageMapper>(inst: &mut Inst, mapper: &RUM) {
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ref mut rt,
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ref mut rt2,
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ref mut mem,
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..
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} => {
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map_def(mapper, rt);
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map_def(mapper, rt2);
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@@ -2979,26 +3048,32 @@ impl Inst {
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&Inst::ULoad8 {
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rd,
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ref mem,
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..
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}
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| &Inst::SLoad8 {
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rd,
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ref mem,
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..
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}
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| &Inst::ULoad16 {
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rd,
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ref mem,
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..
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}
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| &Inst::SLoad16 {
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rd,
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ref mem,
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..
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}
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| &Inst::ULoad32 {
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rd,
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ref mem,
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..
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}
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| &Inst::SLoad32 {
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rd,
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ref mem,
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..
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}
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| &Inst::ULoad64 {
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rd,
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@@ -3035,14 +3110,17 @@ impl Inst {
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&Inst::Store8 {
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rd,
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ref mem,
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..
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}
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| &Inst::Store16 {
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rd,
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ref mem,
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..
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}
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| &Inst::Store32 {
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rd,
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ref mem,
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..
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}
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| &Inst::Store64 {
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rd,
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@@ -3070,13 +3148,13 @@ impl Inst {
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let mem = mem.show_rru(mb_rru);
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format!("{}{} {}, {}", mem_str, op, rd, mem)
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}
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&Inst::StoreP64 { rt, rt2, ref mem } => {
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&Inst::StoreP64 { rt, rt2, ref mem, .. } => {
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let rt = rt.show_rru(mb_rru);
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let rt2 = rt2.show_rru(mb_rru);
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let mem = mem.show_rru(mb_rru);
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format!("stp {}, {}, {}", rt, rt2, mem)
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}
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&Inst::LoadP64 { rt, rt2, ref mem } => {
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&Inst::LoadP64 { rt, rt2, ref mem, .. } => {
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let rt = rt.to_reg().show_rru(mb_rru);
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let rt2 = rt2.to_reg().show_rru(mb_rru);
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let mem = mem.show_rru(mb_rru);
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