Declare constants in the function preamble

This allows us to give names to constants in the constant pool and then use these names in the function body. The original behavior, specifiying the constant value as an instruction immediate, is still supported as a shortcut but some filetests had to change since the canonical way of printing the CLIF constants is now in the preamble.

cranelift/filetests/filetests/isa/x86/simd-arithmetic-legalize.clif

@@ -3,10 +3,12 @@ set enable_simd
 target x86_64 skylake
 
 function %ineg_i32x4() -> b1 {
+; check:  const0 = 0x00000001000000010000000100000001
+; nextln: const1 = 0x00000000000000000000000000000000
 block0:
     v0 = vconst.i32x4 [1 1 1 1]
     v2 = ineg v0
-    ; check: v5 = vconst.i32x4 0x00
+    ; check: v5 = vconst.i32x4 const1
     ; nextln: v2 = isub v5, v0
 
     v3 = extractlane v2, 0
@@ -16,37 +18,39 @@ block0:
 }
 
 function %ineg_legalized() {
+; check: const0 = 0x00000000000000000000000000000000
 block0:
     v0 = vconst.i8x16 0x00
     v1 = ineg v0
-    ; check: v6 = vconst.i8x16 0x00
+    ; check: v6 = vconst.i8x16 const0
     ; nextln: v1 = isub v6, v0
 
     v2 = raw_bitcast.i16x8 v0
     v3 = ineg v2
-    ; check: v7 = vconst.i16x8 0x00
+    ; check: v7 = vconst.i16x8 const0
     ; nextln: v3 = isub v7, v2
 
     v4 = raw_bitcast.i64x2 v0
     v5 = ineg v4
-    ; check: v8 = vconst.i64x2 0x00
+    ; check: v8 = vconst.i64x2 const0
     ; nextln: v5 = isub v8, v4
 
     return
 }
 
 function %fneg_legalized() {
+; check: const2 = 0xffffffffffffffffffffffffffffffff
 block0:
     v0 = vconst.f32x4 [0x1.0 0x2.0 0x3.0 0x4.0]
     v1 = fneg v0
-    ; check: v4 = vconst.i32x4 0xffffffffffffffffffffffffffffffff
+    ; check: v4 = vconst.i32x4 const2
     ; nextln: v5 = ishl_imm v4, 31
     ; nextln: v6 = raw_bitcast.f32x4 v5
     ; nextln: v1 = bxor v0, v6
 
     v2 = vconst.f64x2 [0x1.0 0x2.0]
     v3 = fneg v2
-    ; check: v7 = vconst.i64x2 0xffffffffffffffffffffffffffffffff
+    ; check: v7 = vconst.i64x2 const2
     ; nextln: v8 = ishl_imm v7, 63
     ; nextln: v9 = raw_bitcast.f64x2 v8
     ; nextln: v3 = bxor v2, v9
@@ -55,10 +59,11 @@ block0:
 }
 
 function %fabs_legalized() {
+; check: const1 = 0xffffffffffffffffffffffffffffffff
 block0:
     v0 = vconst.f64x2 [0x1.0 -0x2.0]
     v1 = fabs v0
-    ; check: v2 = vconst.i64x2 0xffffffffffffffffffffffffffffffff
+    ; check: v2 = vconst.i64x2 const1
     ; nextln: v3 = ushr_imm v2, 1
     ; nextln: v4 = raw_bitcast.f64x2 v3
     ; nextln: v1 = band v0, v4

cranelift/filetests/filetests/isa/x86/simd-comparison-legalize.clif

@@ -3,20 +3,22 @@ set enable_simd
 target x86_64 skylake
 
 function %icmp_ne_32x4(i32x4, i32x4) -> b32x4 {
+; check: const0 = 0xffffffffffffffffffffffffffffffff
 block0(v0: i32x4, v1: i32x4):
     v2 = icmp ne v0, v1
     ; check: v3 = icmp eq v0, v1
-    ; nextln: v4 = vconst.b32x4 0xffffffffffffffffffffffffffffffff
+    ; nextln: v4 = vconst.b32x4 const0
     ; nextln: v2 = bxor v4, v3
     return v2
 }
 
 function %icmp_ugt_i32x4(i32x4, i32x4) -> b32x4 {
+; check: const0 = 0xffffffffffffffffffffffffffffffff
 block0(v0: i32x4, v1: i32x4):
     v2 = icmp ugt v0, v1
     ; check: v3 = x86_pmaxu v0, v1
     ; nextln: v4 = icmp eq v3, v1
-    ; nextln: v5 = vconst.b32x4 0xffffffffffffffffffffffffffffffff
+    ; nextln: v5 = vconst.b32x4 const0
     ; nextln: v2 = bxor v5, v4
     return v2
 }

cranelift/filetests/filetests/isa/x86/simd-lane-access-legalize.clif

@@ -5,27 +5,30 @@ target x86_64 skylake
 ;; shuffle
 
 function %shuffle_different_ssa_values() -> i8x16 {
+; check:  const2 = 0x80000000000000000000000000000000
+; nextln: const3 = 0x01808080808080808080808080808080
 block0:
     v0 = vconst.i8x16 0x00
     v1 = vconst.i8x16 0x01
     v2 = shuffle v0, v1, 0x11000000000000000000000000000000     ; pick the second lane of v1, the rest use the first lane of v0
     return v2
 }
-; check:  v1 = vconst.i8x16 0x01
-; nextln: v3 = vconst.i8x16 0x80000000000000000000000000000000
+; check:  v1 = vconst.i8x16 const1
+; nextln: v3 = vconst.i8x16 const2
 ; nextln: v4 = x86_pshufb v0, v3
-; nextln: v5 = vconst.i8x16 0x01808080808080808080808080808080
+; nextln: v5 = vconst.i8x16 const3
 ; nextln: v6 = x86_pshufb v1, v5
 ; nextln: v2 = bor v4, v6
 
 function %shuffle_same_ssa_value() -> i8x16 {
+; check:  const1 = 0x03000000000000000000000000000000
 block0:
     v1 = vconst.i8x16 0x01
     v2 = shuffle v1, v1, 0x13000000000000000000000000000000     ; pick the fourth lane of v1 and the rest from the first lane of v1
     return v2
 }
-; check:  v1 = vconst.i8x16 0x01
-; nextln: v3 = vconst.i8x16 0x03000000000000000000000000000000
+; check:  v1 = vconst.i8x16 const0
+; nextln: v3 = vconst.i8x16 const1
 ; nextln: v2 = x86_pshufb v1, v3
 
 ;; splat
@@ -71,6 +74,7 @@ block0:
 ; nextln:     return v1
 
 function %splat_i8() -> i8x16 {
+; check: const0 = 0x00000000000000000000000000000000
 block0:
     v0 = iconst.i8 42
     v1 = splat.i8x16 v0
@@ -80,16 +84,17 @@ block0:
 ; nextln:     v2 = iconst.i32 42
 ; nextln:     v0 = ireduce.i8 v2
 ; nextln:     v3 = scalar_to_vector.i8x16 v0
-; nextln:     v4 = vconst.i8x16 0x00
+; nextln:     v4 = vconst.i8x16 const0
 ; nextln:     v1 = x86_pshufb v3, v4
 ; nextln:     return v1
 
 function %swizzle() -> i8x16 {
+; check: const1 = 0x70707070707070707070707070707070
 block0:
     v0 = vconst.i8x16 [0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15]
     v1 = vconst.i8x16 [0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15]
     v2 = swizzle.i8x16 v0, v1
-    ; check: v3 = vconst.i8x16 0x70707070707070707070707070707070
+    ; check: v3 = vconst.i8x16 const1
     ; nextln: v4 = uadd_sat v1, v3
     ; nextln: v2 = x86_pshufb v0, v4
     return v2

cranelift/filetests/filetests/isa/x86/simd-logical-legalize.clif

@@ -3,9 +3,10 @@ set enable_simd
 target x86_64 skylake
 
 function %bnot_b32x4(b32x4) -> b32x4 {
+; check: const0 = 0xffffffffffffffffffffffffffffffff
 block0(v0: b32x4):
     v1 = bnot v0
-    ; check: v2 = vconst.b32x4 0xffffffffffffffffffffffffffffffff
+    ; check: v2 = vconst.b32x4 const0
     ; nextln: v1 = bxor v2, v0
     return v1
 }
@@ -19,9 +20,10 @@ block0(v0: b32x4):
 }
 
 function %vall_true_i64x2(i64x2) -> b1 {
+; check: const0 = 0x00000000000000000000000000000000
 block0(v0: i64x2):
     v1 = vall_true v0
-    ; check: v2 = vconst.i64x2 0x00
+    ; check: v2 = vconst.i64x2 const0
     ; nextln: v3 = icmp eq v0, v2
     ; nextln: v4 = x86_ptest v3, v3
     ; nextln: v1 = trueif eq v4

cranelift/filetests/filetests/isa/x86/simd-vconst-binemit.clif

@@ -9,3 +9,13 @@ block0:
 [-, %xmm3]  v1 = vconst.b8x16 0x02  ; bin: 0f 10 1d 00000011 PCRelRodata4(31)
             return
 }
+
+function %vconst_with_preamble() {
+const42 = i32x4 [1 0 0 0]
+const43 = i32x4 [2 0 0 0]
+
+block0:
+[-, %xmm2]  v0 = vconst.i32x4 const42  ; bin: 0f 10 15 00000008 PCRelRodata4(15)
+[-, %xmm3]  v1 = vconst.i32x4 const43  ; bin: 0f 10 1d 00000011 PCRelRodata4(31)
+            return
+}

cranelift/filetests/filetests/isa/x86/simd-vconst-compile.clif

@@ -9,8 +9,8 @@ block0:
     v0 = vconst.i32x4 0x1234
     return v0
 }
-
+; check:   const0 = 0x00000000000000000000000000001234
 ; check:   block0:
-; nextln:     v0 = vconst.i32x4 0x1234
+; nextln:     v0 = vconst.i32x4 const0
 ; nextln:     return v0
 ; nextln: }

cranelift/filetests/filetests/isa/x86/simd-vconst-rodata.clif

@@ -37,3 +37,13 @@ block11:
 }
 
 ; sameln: [1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F, 10]
+
+function %vconst_preamble() -> b16x8 {
+const42 = i32x4 [0 1 2 3]
+const43 = i32x4 [4 5 6 7]
+block0:
+    v0 = vconst.b16x8 const42
+    return v0
+}
+
+; sameln: [0, 0, 0, 0, 1, 0, 0, 0, 2, 0, 0, 0, 3, 0, 0, 0, 4, 0, 0, 0, 5, 0, 0, 0, 6, 0, 0, 0, 7, 0, 0, 0]