Generate binemit::emit_inst() functions.

Use the meta language encoding recipes to generate an emit_inst()
function for each ISA. The generated calls into recipe_*() functions
that must be implemented by hand.

Implement recipe_*() functions for the RISC-V recipes.

Add the TargetIsa::emit_inst() entry point which emits an instruction to
a CodeSink trait object.

lib/cretonne/src/isa/intel/mod.rs

@@ -1,14 +1,16 @@
 //! Intel Instruction Set Architectures.
 
 pub mod settings;
+mod binemit;
 mod enc_tables;
 mod registers;
 
+use binemit::CodeSink;
 use super::super::settings as shared_settings;
 use isa::enc_tables::{self as shared_enc_tables, lookup_enclist, general_encoding};
 use isa::Builder as IsaBuilder;
 use isa::{TargetIsa, RegInfo, Encoding, Legalize, RecipeConstraints};
-use ir::{InstructionData, DataFlowGraph};
+use ir;
 
 #[allow(dead_code)]
 struct Isa {
@@ -53,7 +55,10 @@ impl TargetIsa for Isa {
         registers::INFO.clone()
     }
 
-    fn encode(&self, dfg: &DataFlowGraph, inst: &InstructionData) -> Result<Encoding, Legalize> {
+    fn encode(&self,
+              dfg: &ir::DataFlowGraph,
+              inst: &ir::InstructionData)
+              -> Result<Encoding, Legalize> {
         lookup_enclist(inst.ctrl_typevar(dfg),
                        inst.opcode(),
                        self.cpumode,
@@ -74,4 +79,8 @@ impl TargetIsa for Isa {
     fn recipe_constraints(&self) -> &'static [RecipeConstraints] {
         &enc_tables::RECIPE_CONSTRAINTS
     }
+
+    fn emit_inst(&self, func: &ir::Function, inst: ir::Inst, sink: &mut CodeSink) {
+        binemit::emit_inst(func, inst, sink)
+    }
 }