Define register classes for 4 ISAs.

2016-11-11 15:08:12 -08:00
parent e1c0171b2c
commit 060735adfe
5 changed files with 70 additions and 5 deletions
--- a/lib/cretonne/meta/isa/arm64/registers.py
+++ b/lib/cretonne/meta/isa/arm64/registers.py
@@ -2,7 +2,7 @@
 Aarch64 register banks.
 """
 from __future__ import absolute_import
-from cdsl.registers import RegBank
+from cdsl.registers import RegBank, RegClass
 from .defs import ISA


@@ -17,3 +17,6 @@ FloatRegs = RegBank(
        'FloatRegs', ISA,
        'Floating point registers',
        units=32, prefix='v')
+
+GPR = RegClass('GPR', IntRegs)
+FPR = RegClass('FPR', FloatRegs)