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Cranelift: use regalloc2 constraints on caller side of ABI code. (#4892)

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* Cranelift: use regalloc2 constraints on caller side of ABI code.

This PR updates the shared ABI code and backends to use register-operand
constraints rather than explicit pinned-vreg moves for register
arguments and return values.

The s390x backend was not updated, because it has its own implementation
of ABI code. Ideally we could converge back to the code shared by x64
and aarch64 (which didn't exist when s390x ported calls to ISLE, so the
current situation is underestandable, to be clear!). I'll leave this for
future work.

This PR exposed several places where regalloc2 needed to be a bit more
flexible with constraints; it requires regalloc2#74 to be merged and
pulled in.

* Update to regalloc2 0.3.3.

In addition to version bump, this required removing two asserts as
`SpillSlot`s no longer carry their class (so we can't assert that they
have the correct class).

* Review comments.

* Filetest updates.

* Add cargo-vet audit for regalloc2 0.3.2 -> 0.3.3 upgrade.

* Update to regalloc2 0.4.0.
This commit is contained in:
Chris Fallin
2022-09-20 18:17:04 -07:00
committed by GitHub
parent 8b245178a5
commit 05cbd667c7
63 changed files with 1476 additions and 1177 deletions
Download Patch File Download Diff File Expand all files Collapse all files

25
cranelift/codegen/src/isa/aarch64/abi.rs
View File

@@ -919,8 +919,8 @@ impl ABIMachineSpec for AArch64MachineDeps {
fn gen_call(
dest: &CallDest,
uses: SmallVec<[Reg; 8]>,
defs: SmallVec<[Writable<Reg>; 8]>,
uses: CallArgList,
defs: CallRetList,
clobbers: PRegSet,
opcode: ir::Opcode,
tmp: Writable<Reg>,
@@ -978,19 +978,32 @@ impl ABIMachineSpec for AArch64MachineDeps {
call_conv: isa::CallConv,
dst: Reg,
src: Reg,
tmp: Writable<Reg>,
_tmp2: Writable<Reg>,
size: usize,
) -> SmallVec<[Self::I; 8]> {
let mut insts = SmallVec::new();
let arg0 = writable_xreg(0);
let arg1 = writable_xreg(1);
let arg2 = writable_xreg(2);
insts.push(Inst::gen_move(arg0, dst, I64));
insts.push(Inst::gen_move(arg1, src, I64));
insts.extend(Inst::load_constant(arg2, size as u64).into_iter());
insts.extend(Inst::load_constant(tmp, size as u64).into_iter());
insts.push(Inst::Call {
info: Box::new(CallInfo {
dest: ExternalName::LibCall(LibCall::Memcpy),
uses: smallvec![arg0.to_reg(), arg1.to_reg(), arg2.to_reg()],
uses: smallvec![
CallArgPair {
vreg: dst,
preg: arg0.to_reg()
},
CallArgPair {
vreg: src,
preg: arg1.to_reg()
},
CallArgPair {
vreg: tmp.to_reg(),
preg: arg2.to_reg()
}
],
defs: smallvec![],
clobbers: Self::get_regs_clobbered_by_call(call_conv),
opcode: Opcode::Call,

24
cranelift/codegen/src/isa/aarch64/inst/mod.rs
View File

@@ -78,8 +78,8 @@ impl BitOp {
#[derive(Clone, Debug)]
pub struct CallInfo {
pub dest: ExternalName,
pub uses: SmallVec<[Reg; 8]>,
pub defs: SmallVec<[Writable<Reg>; 8]>,
pub uses: CallArgList,
pub defs: CallRetList,
pub clobbers: PRegSet,
pub opcode: Opcode,
pub caller_callconv: CallConv,
@@ -91,8 +91,8 @@ pub struct CallInfo {
#[derive(Clone, Debug)]
pub struct CallIndInfo {
pub rn: Reg,
pub uses: SmallVec<[Reg; 8]>,
pub defs: SmallVec<[Writable<Reg>; 8]>,
pub uses: SmallVec<[CallArgPair; 8]>,
pub defs: SmallVec<[CallRetPair; 8]>,
pub clobbers: PRegSet,
pub opcode: Opcode,
pub caller_callconv: CallConv,
@@ -1027,14 +1027,22 @@ fn aarch64_get_operands<F: Fn(VReg) -> VReg>(inst: &Inst, collector: &mut Operan
}
&Inst::Jump { .. } => {}
&Inst::Call { ref info, .. } => {
collector.reg_uses(&info.uses[..]);
collector.reg_defs(&info.defs[..]);
for u in &info.uses {
collector.reg_fixed_use(u.vreg, u.preg);
}
for d in &info.defs {
collector.reg_fixed_def(d.vreg, d.preg);
}
collector.reg_clobbers(info.clobbers);
}
&Inst::CallInd { ref info, .. } => {
collector.reg_use(info.rn);
collector.reg_uses(&info.uses[..]);
collector.reg_defs(&info.defs[..]);
for u in &info.uses {
collector.reg_fixed_use(u.vreg, u.preg);
}
for d in &info.defs {
collector.reg_fixed_def(d.vreg, d.preg);
}
collector.reg_clobbers(info.clobbers);
}
&Inst::CondBr { ref kind, .. } => match kind {

6
cranelift/codegen/src/isa/s390x/abi.rs
View File

@@ -743,8 +743,8 @@ impl ABIMachineSpec for S390xMachineDeps {
fn gen_call(
_dest: &CallDest,
_uses: SmallVec<[Reg; 8]>,
_defs: SmallVec<[Writable<Reg>; 8]>,
_uses: CallArgList,
_defs: CallRetList,
_clobbers: PRegSet,
_opcode: ir::Opcode,
_tmp: Writable<Reg>,
@@ -758,6 +758,8 @@ impl ABIMachineSpec for S390xMachineDeps {
_call_conv: isa::CallConv,
_dst: Reg,
_src: Reg,
_tmp1: Writable<Reg>,
_tmp2: Writable<Reg>,
_size: usize,
) -> SmallVec<[Self::I; 8]> {
unimplemented!("StructArgs not implemented for S390X yet");

44
cranelift/codegen/src/isa/x64/abi.rs
View File

@@ -429,7 +429,9 @@ impl ABIMachineSpec for X64ABIMachineSpec {
insts.push(Inst::CallKnown {
dest: ExternalName::LibCall(LibCall::Probestack),
info: Box::new(CallInfo {
uses: smallvec![regs::rax()],
// No need to include arg here: we are post-regalloc
// so no constraints will be seen anyway.
uses: smallvec![],
defs: smallvec![],
clobbers: PRegSet::empty(),
opcode: Opcode::Call,
@@ -584,8 +586,8 @@ impl ABIMachineSpec for X64ABIMachineSpec {
/// Generate a call instruction/sequence.
fn gen_call(
dest: &CallDest,
uses: SmallVec<[Reg; 8]>,
defs: SmallVec<[Writable<Reg>; 8]>,
uses: CallArgList,
defs: CallRetList,
clobbers: PRegSet,
opcode: ir::Opcode,
tmp: Writable<Reg>,
@@ -628,39 +630,47 @@ impl ABIMachineSpec for X64ABIMachineSpec {
call_conv: isa::CallConv,
dst: Reg,
src: Reg,
temp: Writable<Reg>,
temp2: Writable<Reg>,
size: usize,
) -> SmallVec<[Self::I; 8]> {
let mut insts = SmallVec::new();
let arg0 = get_intreg_for_arg(&call_conv, 0, 0).unwrap();
let arg1 = get_intreg_for_arg(&call_conv, 1, 1).unwrap();
let arg2 = get_intreg_for_arg(&call_conv, 2, 2).unwrap();
// We need a register to load the address of `memcpy()` below and we
// don't have a lowering context to allocate a temp here; so just use a
// register we know we are free to mutate as part of this sequence
// (because it is clobbered by the call as per the ABI anyway).
let memcpy_addr = get_intreg_for_arg(&call_conv, 3, 3).unwrap();
insts.push(Inst::gen_move(Writable::from_reg(arg0), dst, I64));
insts.push(Inst::gen_move(Writable::from_reg(arg1), src, I64));
insts.extend(
Inst::gen_constant(
ValueRegs::one(Writable::from_reg(arg2)),
size as u128,
I64,
|_| panic!("tmp should not be needed"),
)
Inst::gen_constant(ValueRegs::one(temp), size as u128, I64, |_| {
panic!("tmp should not be needed")
})
.into_iter(),
);
// We use an indirect call and a full LoadExtName because we do not have
// information about the libcall `RelocDistance` here, so we
// conservatively use the more flexible calling sequence.
insts.push(Inst::LoadExtName {
dst: Writable::from_reg(memcpy_addr),
dst: temp2,
name: Box::new(ExternalName::LibCall(LibCall::Memcpy)),
offset: 0,
});
insts.push(Inst::call_unknown(
RegMem::reg(memcpy_addr),
/* uses = */ smallvec![arg0, arg1, arg2],
RegMem::reg(temp2.to_reg()),
/* uses = */
smallvec![
CallArgPair {
vreg: dst,
preg: arg0
},
CallArgPair {
vreg: src,
preg: arg1
},
CallArgPair {
vreg: temp.to_reg(),
preg: arg2
},
],
/* defs = */ smallvec![],
/* clobbers = */ Self::get_regs_clobbered_by_call(call_conv),
Opcode::Call,

41
cranelift/codegen/src/isa/x64/inst/mod.rs
View File

@@ -1,7 +1,7 @@
//! This module defines x86_64-specific machine instruction types.
use crate::binemit::{Addend, CodeOffset, Reloc, StackMap};
use crate::ir::{types, ExternalName, Opcode, RelSourceLoc, TrapCode, Type};
use crate::ir::{types, ExternalName, LibCall, Opcode, RelSourceLoc, TrapCode, Type};
use crate::isa::x64::abi::X64ABIMachineSpec;
use crate::isa::x64::inst::regs::pretty_print_reg;
use crate::isa::x64::settings as x64_settings;
@@ -34,9 +34,9 @@ pub use super::lower::isle::generated_code::MInst as Inst;
#[derive(Clone, Debug)]
pub struct CallInfo {
/// Register uses of this call.
pub uses: SmallVec<[Reg; 8]>,
pub uses: CallArgList,
/// Register defs of this call.
pub defs: SmallVec<[Writable<Reg>; 8]>,
pub defs: CallRetList,
/// Registers clobbered by this call, as per its calling convention.
pub clobbers: PRegSet,
/// The opcode of this call.
@@ -490,8 +490,8 @@ impl Inst {
pub(crate) fn call_known(
dest: ExternalName,
uses: SmallVec<[Reg; 8]>,
defs: SmallVec<[Writable<Reg>; 8]>,
uses: CallArgList,
defs: CallRetList,
clobbers: PRegSet,
opcode: Opcode,
) -> Inst {
@@ -508,8 +508,8 @@ impl Inst {
pub(crate) fn call_unknown(
dest: RegMem,
uses: SmallVec<[Reg; 8]>,
defs: SmallVec<[Writable<Reg>; 8]>,
uses: CallArgList,
defs: CallRetList,
clobbers: PRegSet,
opcode: Opcode,
) -> Inst {
@@ -1446,7 +1446,9 @@ impl PrettyPrint for Inst {
format!("{} {}", ljustify("popq".to_string()), dst)
}
Inst::CallKnown { dest, .. } => format!("{} {:?}", ljustify("call".to_string()), dest),
Inst::CallKnown { dest, .. } => {
format!("{} {:?}", ljustify("call".to_string()), dest)
}
Inst::CallUnknown { dest, .. } => {
let dest = dest.pretty_print(8, allocs);
@@ -1981,23 +1983,28 @@ fn x64_get_operands<F: Fn(VReg) -> VReg>(inst: &Inst, collector: &mut OperandCol
collector.reg_early_def(*tmp);
}
Inst::CallKnown { ref info, .. } => {
for &u in &info.uses {
collector.reg_use(u);
Inst::CallKnown { dest, ref info, .. } => {
// Probestack is special and is only inserted after
// regalloc, so we do not need to represent its ABI to the
// register allocator. Assert that we don't alter that
// arrangement.
debug_assert_ne!(*dest, ExternalName::LibCall(LibCall::Probestack));
for u in &info.uses {
collector.reg_fixed_use(u.vreg, u.preg);
}
for &d in &info.defs {
collector.reg_def(d);
for d in &info.defs {
collector.reg_fixed_def(d.vreg, d.preg);
}
collector.reg_clobbers(info.clobbers);
}
Inst::CallUnknown { ref info, dest, .. } => {
dest.get_operands(collector);
for &u in &info.uses {
collector.reg_use(u);
for u in &info.uses {
collector.reg_fixed_use(u.vreg, u.preg);
}
for &d in &info.defs {
collector.reg_def(d);
for d in &info.defs {
collector.reg_fixed_def(d.vreg, d.preg);
}
collector.reg_clobbers(info.clobbers);
}

15
cranelift/codegen/src/isa/x64/lower.rs
View File

@@ -8,11 +8,12 @@ use crate::isa::x64::abi::*;
use crate::isa::x64::inst::args::*;
use crate::isa::x64::inst::*;
use crate::isa::{x64::settings as x64_settings, x64::X64Backend, CallConv};
use crate::machinst::abi::SmallInstVec;
use crate::machinst::lower::*;
use crate::machinst::*;
use crate::result::CodegenResult;
use crate::settings::Flags;
use smallvec::SmallVec;
use smallvec::{smallvec, SmallVec};
use target_lexicon::Triple;
//=============================================================================
@@ -168,16 +169,18 @@ fn emit_vm_call(
assert_eq!(inputs.len(), abi.num_args(ctx.sigs()));
for (i, input) in inputs.iter().enumerate() {
for inst in abi.gen_copy_regs_to_arg(ctx, i, ValueRegs::one(*input)) {
for inst in abi.gen_arg(ctx, i, ValueRegs::one(*input)) {
ctx.emit(inst);
}
}
abi.emit_call(ctx);
let mut retval_insts: SmallInstVec<_> = smallvec![];
for (i, output) in outputs.iter().enumerate() {
for inst in abi.gen_copy_retval_to_regs(ctx, i, ValueRegs::one(*output)) {
ctx.emit(inst);
}
retval_insts.extend(abi.gen_retval(ctx, i, ValueRegs::one(*output)).into_iter());
}
abi.emit_call(ctx);
for inst in retval_insts {
ctx.emit(inst);
}
abi.emit_stack_post_adjust(ctx);