Rename "Stackmap" to "StackMap"
And "stackmap" to "stack_map". This commit is purely mechanical.
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@@ -10,7 +10,7 @@
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//! single ISA instance.
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use crate::binemit::{
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relax_branches, shrink_instructions, CodeInfo, MemoryCodeSink, RelocSink, StackmapSink,
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relax_branches, shrink_instructions, CodeInfo, MemoryCodeSink, RelocSink, StackMapSink,
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TrapSink,
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};
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use crate::dce::do_dce;
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@@ -127,13 +127,19 @@ impl Context {
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mem: &mut Vec<u8>,
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relocs: &mut dyn RelocSink,
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traps: &mut dyn TrapSink,
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stackmaps: &mut dyn StackmapSink,
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stack_maps: &mut dyn StackMapSink,
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) -> CodegenResult<CodeInfo> {
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let info = self.compile(isa)?;
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let old_len = mem.len();
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mem.resize(old_len + info.total_size as usize, 0);
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let new_info = unsafe {
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self.emit_to_memory(isa, mem.as_mut_ptr().add(old_len), relocs, traps, stackmaps)
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self.emit_to_memory(
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isa,
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mem.as_mut_ptr().add(old_len),
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relocs,
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traps,
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stack_maps,
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)
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};
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debug_assert!(new_info == info);
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Ok(info)
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@@ -222,10 +228,10 @@ impl Context {
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mem: *mut u8,
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relocs: &mut dyn RelocSink,
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traps: &mut dyn TrapSink,
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stackmaps: &mut dyn StackmapSink,
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stack_maps: &mut dyn StackMapSink,
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) -> CodeInfo {
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let _tt = timing::binemit();
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let mut sink = MemoryCodeSink::new(mem, relocs, traps, stackmaps);
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let mut sink = MemoryCodeSink::new(mem, relocs, traps, stack_maps);
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if let Some(ref result) = &self.mach_compile_result {
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result.buffer.emit(&mut sink);
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} else {
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