Add Intel encodings for more conversion instructions.

The following instructions have simple encodings:

- bitcast.f32.i32
- bitcast.i32.f32
- bitcast.f64.i64
- bitcast.i64.f64
- fpromote.f64.f32
- fdemote.f32.f64

Also add helper functions enc_flt() and enc_i32_i64 to
intel.encodings.py for generating the common set of encodings for an
instruction: I32, I64 w/REX, I64 w/o REX.

lib/cretonne/meta/isa/intel/recipes.py

@@ -232,6 +232,14 @@ umr = TailRecipe(
         modrm_rr(out_reg0, in_reg0, sink);
         ''')
 
+# Same as umr, but with FPR -> GPR registers.
+rfumr = TailRecipe(
+        'rfumr', Unary, size=1, ins=FPR, outs=GPR,
+        emit='''
+        PUT_OP(bits, rex2(out_reg0, in_reg0), sink);
+        modrm_rr(out_reg0, in_reg0, sink);
+        ''')
+
 # XX /r, but for a unary operator with separate input/output register.
 # RM form.
 urm = TailRecipe(
@@ -249,9 +257,17 @@ urm_abcd = TailRecipe(
         modrm_rr(in_reg0, out_reg0, sink);
         ''')
 
-# XX /r, RM form, GPR -> FPR.
+# XX /r, RM form, FPR -> FPR.
 furm = TailRecipe(
-        'furm', Unary, size=1, ins=GPR, outs=FPR,
+        'furm', Unary, size=1, ins=FPR, outs=FPR,
+        emit='''
+        PUT_OP(bits, rex2(in_reg0, out_reg0), sink);
+        modrm_rr(in_reg0, out_reg0, sink);
+        ''')
+
+# XX /r, RM form, GPR -> FPR.
+frurm = TailRecipe(
+        'frurm', Unary, size=1, ins=GPR, outs=FPR,
         emit='''
         PUT_OP(bits, rex2(in_reg0, out_reg0), sink);
         modrm_rr(in_reg0, out_reg0, sink);