T0b1/wasmtime
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Adds f32.mul, f32.div for vcode backend for x64.

Browse Source 
Adds support for lowering clif instructions Fdiv and Fmul
for new vcode backend. Misc adds lowering and test for
sqrtss and removes a redundant to_string() func for the
SseOpcode struct.
This commit is contained in:
Johnnie Birch
2020-06-01 00:39:31 -07:00
parent 4f72a7483b
commit 043571fee0
4 changed files with 31 additions and 24 deletions
Download Patch File Download Diff File Expand all files Collapse all files

14
cranelift/codegen/src/isa/x64/lower.rs
View File

@@ -194,16 +194,19 @@ fn lower_insn_to_regs<'a>(ctx: Ctx<'a>, inst: IRInst) {
// N.B.: the Ret itself is generated by the ABI.
}
Opcode::Fadd | Opcode::Fsub => {
Opcode::Fadd | Opcode::Fsub | Opcode::Fmul | Opcode::Fdiv => {
let dst = output_to_reg(ctx, inst, 0);
let lhs = input_to_reg(ctx, inst, 0);
let rhs = input_to_reg(ctx, inst, 1);
let is_64 = flt_ty_is_64(ty.unwrap());
if !is_64 {
let sse_op = if op == Opcode::Fadd {
SseOpcode::Addss
} else {
SseOpcode::Subss
let sse_op = match op {
Opcode::Fadd => SseOpcode::Addss,
Opcode::Fsub => SseOpcode::Subss,
Opcode::Fmul => SseOpcode::Mulss,
Opcode::Fdiv => SseOpcode::Divss,
// TODO Fmax, Fmin.
_ => unimplemented!(),
};
ctx.emit(Inst::xmm_r_r(SseOpcode::Movss, lhs, dst));
ctx.emit(Inst::xmm_rm_r(sse_op, RegMem::reg(rhs), dst));
@@ -241,7 +244,6 @@ fn lower_insn_to_regs<'a>(ctx: Ctx<'a>, inst: IRInst) {
| Opcode::SshrImm => {
panic!("ALU+imm and ALU+carry ops should not appear here!");
}
_ => unimplemented!("unimplemented lowering for opcode {:?}", op),
}
}