ISLE: remove all uses of argument polarity, and remove it from the language. (#4091)
This PR removes "argument polarity": the feature of ISLE extractors that lets them take inputs aside from the value to be matched. Cases that need this expressivity have been subsumed by #4072 with if-let clauses; we can now finally remove this misfeature of the language, which has caused significant confusion and has always felt like a bit of a hack. This PR (i) removes the feature from the ISLE compiler; (ii) removes it from the reference documentation; and (iii) refactors away all uses of the feature in our three existing backends written in ISLE.
This commit is contained in:
Chris Fallin
@@ -937,14 +937,18 @@
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;; Detect specific integer values
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(decl i64_nonequal (i64 i64) i64)
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(extern extractor i64_nonequal i64_nonequal (out in))
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(decl pure i64_nonequal (i64 i64) i64)
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(extern constructor i64_nonequal i64_nonequal)
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(decl i64_nonzero (i64) i64)
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(extractor (i64_nonzero val) (i64_nonequal val <0))
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(decl pure i64_nonzero (i64) i64)
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(rule (i64_nonzero x)
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(if (i64_nonequal x 0))
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x)
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(decl i64_not_neg1 (i64) i64)
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(extractor (i64_not_neg1 val) (i64_nonequal val <-1))
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(decl pure i64_not_neg1 (i64) i64)
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(rule (i64_not_neg1 x)
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(if (i64_nonequal x -1))
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x)
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;; Integer type casts (with the rust `as` semantics).
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@@ -1116,12 +1120,13 @@
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;; Form the sum of two offset values, and check that the result is
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;; a valid `MemArg::Symbol` offset (i.e. is even and fits into i32).
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(decl memarg_symbol_offset_sum (i64 i32) i64)
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(extern extractor memarg_symbol_offset_sum memarg_symbol_offset_sum (in out))
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(decl pure memarg_symbol_offset_sum (i64 i64) i32)
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(extern constructor memarg_symbol_offset_sum memarg_symbol_offset_sum)
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;; Likewise, but just check a single offset value.
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(decl memarg_symbol_offset (i32) i64)
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(extractor (memarg_symbol_offset offset) (memarg_symbol_offset_sum <0 offset))
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(decl pure memarg_symbol_offset (i64) i32)
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(rule (memarg_symbol_offset x)
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(memarg_symbol_offset_sum x 0))
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;; Lower an address into a `MemArg`.
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@@ -1130,29 +1135,33 @@
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(rule (lower_address flags addr (i64_from_offset offset))
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(memarg_reg_plus_off addr offset flags))
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(rule (lower_address flags (def_inst (iadd x y)) (i64_from_offset 0))
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(rule (lower_address flags (iadd x y) (i64_from_offset 0))
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(memarg_reg_plus_reg x y flags))
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(rule (lower_address flags
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(def_inst (symbol_value (symbol_value_data name (reloc_distance_near) offset)))
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(i64_from_offset (memarg_symbol_offset_sum <offset final_offset)))
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(symbol_value (symbol_value_data name (reloc_distance_near) sym_offset))
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(i64_from_offset offset))
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(if-let final_offset (memarg_symbol_offset_sum offset sym_offset))
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(memarg_symbol name final_offset flags))
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;; Test whether a `load` address will be lowered to a `MemArg::Symbol`.
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(decl load_sym (Inst) Inst)
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(extractor (load_sym inst)
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(and inst
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(load _ (def_inst (symbol_value (symbol_value_data _ (reloc_distance_near) offset)))
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(i64_from_offset (memarg_symbol_offset_sum <offset _)))))
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(decl uload16_sym (Inst) Inst)
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(extractor (uload16_sym inst)
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(and inst
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(uload16 _ (def_inst (symbol_value (symbol_value_data _ (reloc_distance_near) offset)))
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(i64_from_offset (memarg_symbol_offset_sum <offset _)))))
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(decl pure load_sym (Inst) Inst)
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(rule (load_sym inst)
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(if-let (load _ (symbol_value (symbol_value_data _ (reloc_distance_near) sym_offset))
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(i64_from_offset load_offset))
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inst)
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(if (memarg_symbol_offset_sum sym_offset load_offset))
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inst)
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(decl pure uload16_sym (Inst) Inst)
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(rule (uload16_sym inst)
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(if-let (uload16 _ (symbol_value (symbol_value_data _ (reloc_distance_near) sym_offset))
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(i64_from_offset load_offset))
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inst)
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(if (memarg_symbol_offset_sum sym_offset load_offset))
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inst)
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;; Helpers for stack-slot addresses ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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@@ -1170,11 +1179,11 @@
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;; A value that is the result of a sign-extend from a 32-bit value.
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(decl sext32_value (Value) Value)
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(extractor (sext32_value x) (def_inst (sextend (and x (value_type $I32)))))
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(extractor (sext32_value x) (sextend (and x (value_type $I32))))
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;; A value that is the result of a zero-extend from a 32-bit value.
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(decl zext32_value (Value) Value)
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(extractor (zext32_value x) (def_inst (uextend (and x (value_type $I32)))))
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(extractor (zext32_value x) (uextend (and x (value_type $I32))))
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;; Helpers for sinkable loads ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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@@ -1777,8 +1786,8 @@
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;; Similarly, because we cannot allocate temp registers, if an instruction
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;; requires matching source and destination registers, this needs to be handled
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;; by the user. Another helper to verify that constraint.
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(decl same_reg (WritableReg) Reg)
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(extern extractor same_reg same_reg (in))
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(decl pure same_reg (WritableReg Reg) Reg)
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(extern constructor same_reg same_reg)
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;; Push a `MInst.AluRRR` instruction to a sequence.
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(decl push_alu_reg (VecMInstBuilder ALUOp WritableReg Reg Reg) Reg)
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@@ -1788,7 +1797,8 @@
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;; Push a `MInst.AluRUImm32Shifted` instruction to a sequence.
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(decl push_alu_uimm32shifted (VecMInstBuilder ALUOp WritableReg Reg UImm32Shifted) Reg)
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(rule (push_alu_uimm32shifted ib op (real_reg dst) (same_reg <dst) imm)
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(rule (push_alu_uimm32shifted ib op (real_reg dst) r imm)
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(if (same_reg dst r))
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(let ((_ Unit (inst_builder_push ib (MInst.AluRUImm32Shifted op dst imm))))
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dst))
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@@ -1801,7 +1811,8 @@
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;; Push a `MInst.RxSBG` instruction to a sequence.
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(decl push_rxsbg (VecMInstBuilder RxSBGOp WritableReg Reg Reg u8 u8 i8) Reg)
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(rule (push_rxsbg ib op (real_reg dst) (same_reg <dst) src start_bit end_bit rotate_amt)
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(rule (push_rxsbg ib op (real_reg dst) r src start_bit end_bit rotate_amt)
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(if (same_reg dst r))
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(let ((_ Unit (inst_builder_push ib
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(MInst.RxSBG op dst src start_bit end_bit rotate_amt))))
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dst))
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@@ -2088,9 +2099,9 @@
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(rule (emit_put_in_reg_zext32 dst (and (value_type (fits_in_16 ty)) (sinkable_load load)))
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(emit_zext32_mem dst ty (sink_load load)))
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(rule (emit_put_in_reg_zext32 dst val @ (value_type (fits_in_16 ty)))
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(emit_zext32_reg dst ty (put_in_reg val)))
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(emit_zext32_reg dst ty val))
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(rule (emit_put_in_reg_zext32 dst val @ (value_type (ty_32_or_64 ty)))
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(emit_mov ty dst (put_in_reg val)))
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(emit_mov ty dst val))
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;; Place `Value` into destination, sign-extending to 32 bits if smaller. (Non-SSA form.)
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(decl emit_put_in_reg_sext32 (WritableReg Value) Unit)
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@@ -2099,9 +2110,9 @@
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(rule (emit_put_in_reg_sext32 dst (and (value_type (fits_in_16 ty)) (sinkable_load load)))
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(emit_sext32_mem dst ty (sink_load load)))
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(rule (emit_put_in_reg_sext32 dst val @ (value_type (fits_in_16 ty)))
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(emit_sext32_reg dst ty (put_in_reg val)))
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(emit_sext32_reg dst ty val))
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(rule (emit_put_in_reg_sext32 dst val @ (value_type (ty_32_or_64 ty)))
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(emit_mov ty dst (put_in_reg val)))
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(emit_mov ty dst val))
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;; Place `Value` into destination, zero-extending to 64 bits if smaller. (Non-SSA form.)
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(decl emit_put_in_reg_zext64 (WritableReg Value) Unit)
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@@ -2110,9 +2121,9 @@
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(rule (emit_put_in_reg_zext64 dst (and (value_type (gpr32_ty ty)) (sinkable_load load)))
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(emit_zext64_mem dst ty (sink_load load)))
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(rule (emit_put_in_reg_zext64 dst val @ (value_type (gpr32_ty ty)))
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(emit_zext64_reg dst ty (put_in_reg val)))
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(emit_zext64_reg dst ty val))
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(rule (emit_put_in_reg_zext64 dst val @ (value_type (gpr64_ty ty)))
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(emit_mov ty dst (put_in_reg val)))
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(emit_mov ty dst val))
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;; Place `Value` into destination, sign-extending to 64 bits if smaller. (Non-SSA form.)
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(decl emit_put_in_reg_sext64 (WritableReg Value) Unit)
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@@ -2121,9 +2132,9 @@
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(rule (emit_put_in_reg_sext64 dst (and (value_type (gpr32_ty ty)) (sinkable_load load)))
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(emit_sext64_mem dst ty (sink_load load)))
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(rule (emit_put_in_reg_sext64 dst val @ (value_type (gpr32_ty ty)))
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(emit_sext64_reg dst ty (put_in_reg val)))
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(emit_sext64_reg dst ty val))
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(rule (emit_put_in_reg_sext64 dst val @ (value_type (gpr64_ty ty)))
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(emit_mov ty dst (put_in_reg val)))
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(emit_mov ty dst val))
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;; Place `Value` into a register, zero-extending to 32 bits if smaller.
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(decl put_in_reg_zext32 (Value) Reg)
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@@ -2132,9 +2143,9 @@
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(rule (put_in_reg_zext32 (and (value_type (fits_in_16 ty)) (sinkable_load load)))
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(zext32_mem ty (sink_load load)))
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(rule (put_in_reg_zext32 val @ (value_type (fits_in_16 ty)))
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(zext32_reg ty (put_in_reg val)))
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(zext32_reg ty val))
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(rule (put_in_reg_zext32 val @ (value_type (ty_32_or_64 _ty)))
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(put_in_reg val))
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val)
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;; Place `Value` into a register, sign-extending to 32 bits if smaller.
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(decl put_in_reg_sext32 (Value) Reg)
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@@ -2143,9 +2154,9 @@
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(rule (put_in_reg_sext32 (and (value_type (fits_in_16 ty)) (sinkable_load load)))
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(sext32_mem ty (sink_load load)))
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(rule (put_in_reg_sext32 val @ (value_type (fits_in_16 ty)))
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(sext32_reg ty (put_in_reg val)))
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(sext32_reg ty val))
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(rule (put_in_reg_sext32 val @ (value_type (ty_32_or_64 _ty)))
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(put_in_reg val))
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val)
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;; Place `Value` into a register, zero-extending to 64 bits if smaller.
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(decl put_in_reg_zext64 (Value) Reg)
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@@ -2154,9 +2165,9 @@
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(rule (put_in_reg_zext64 (and (value_type (gpr32_ty ty)) (sinkable_load load)))
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(zext64_mem ty (sink_load load)))
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(rule (put_in_reg_zext64 val @ (value_type (gpr32_ty ty)))
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(zext64_reg ty (put_in_reg val)))
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(zext64_reg ty val))
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(rule (put_in_reg_zext64 val @ (value_type (gpr64_ty ty)))
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(put_in_reg val))
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val)
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;; Place `Value` into a register, sign-extending to 64 bits if smaller.
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(decl put_in_reg_sext64 (Value) Reg)
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@@ -2165,9 +2176,9 @@
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(rule (put_in_reg_sext64 (and (value_type (gpr32_ty ty)) (sinkable_load load)))
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(sext64_mem ty (sink_load load)))
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(rule (put_in_reg_sext64 val @ (value_type (gpr32_ty ty)))
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(sext64_reg ty (put_in_reg val)))
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(sext64_reg ty val))
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(rule (put_in_reg_sext64 val @ (value_type (gpr64_ty ty)))
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(put_in_reg val))
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val)
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;; Place `Value` into the low half of a register pair, zero-extending
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;; to 32 bits if smaller. The high half is taken from the input.
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