Implement Extractlane, UaddSat, and UsubSat for Cranelift interpreter (#3188)

* Implement `Extractlane`, `UaddSat`, and `UsubSat` for Cranelift interpreter

Implemented the `Extractlane`, `UaddSat`, and `UsubSat` opcodes for the interpreter,
and added helper functions for working with SIMD vectors (`extractlanes`, `vectorizelanes`,
and `binary_arith`).

Copyright (c) 2021, Arm Limited

* Re-use tests + constrict Vector assert

- Re-use interpreter tests as runtests where supported.
- Constrict Vector assertion.
- Code style adjustments following feedback.

Copyright (c) 2021, Arm Limited

* Runtest `i32x4` vectors on AArch64; add `i64x2` tests

Copyright (c) 2021, Arm Limited

* Add `simd-` prefix to test filenames

Copyright (c) 2021, Arm Limited

* Return aliased `SmallVec` from `extractlanes`

Using a `SmallVec<[i128; 4]>` allows larger-width 128-bit vectors
(`i32x4`, `i64x2`, ...) to not cause heap allocations.

Copyright (c) 2021, Arm Limited

* Accept slice to `vectorizelanes` rather than `Vec`

Copyright (c) 2021, Arm Limited

cranelift/filetests/filetests/runtests/simd-usubsat.clif

@@ -0,0 +1,20 @@
+test interpret
+test run
+target aarch64
+set enable_simd
+target x86_64
+
+function %usubsat_i8x16(i8x16, i8x16) -> i8x16 {
+block0(v0: i8x16, v1: i8x16):
+    v2 = usub_sat v0, v1
+    return v2
+}
+; run: %usubsat_i8x16([150 150 150 150 150 150 150 150 150 150 150 150 150 150 150 150], [100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100]) == [50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50]
+; run: %usubsat_i8x16([150 150 150 150 150 150 150 150 150 150 150 150 150 150 150 150], [200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200]) == [0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0]
+
+function %usubsat_i16x8(i16x8, i16x8) -> i16x8 {
+block0(v0: i16x8, v1: i16x8):
+    v2 = usub_sat v0, v1
+    return v2
+}
+; run: %usubsat_i16x8([65534 65534 65534 65534 65534 65534 65534 65534], [65535 65535 65535 65535 65535 65535 65535 65535]) == [0 0 0 0 0 0 0 0]