Implement Extractlane, UaddSat, and UsubSat for Cranelift interpreter (#3188)

* Implement `Extractlane`, `UaddSat`, and `UsubSat` for Cranelift interpreter

Implemented the `Extractlane`, `UaddSat`, and `UsubSat` opcodes for the interpreter,
and added helper functions for working with SIMD vectors (`extractlanes`, `vectorizelanes`,
and `binary_arith`).

Copyright (c) 2021, Arm Limited

* Re-use tests + constrict Vector assert

- Re-use interpreter tests as runtests where supported.
- Constrict Vector assertion.
- Code style adjustments following feedback.

Copyright (c) 2021, Arm Limited

* Runtest `i32x4` vectors on AArch64; add `i64x2` tests

Copyright (c) 2021, Arm Limited

* Add `simd-` prefix to test filenames

Copyright (c) 2021, Arm Limited

* Return aliased `SmallVec` from `extractlanes`

Using a `SmallVec<[i128; 4]>` allows larger-width 128-bit vectors
(`i32x4`, `i64x2`, ...) to not cause heap allocations.

Copyright (c) 2021, Arm Limited

* Accept slice to `vectorizelanes` rather than `Vec`

Copyright (c) 2021, Arm Limited

cranelift/filetests/filetests/runtests/simd-extractlane.clif

@@ -0,0 +1,34 @@
+test interpret
+test run
+target aarch64
+set enable_simd
+target x86_64
+
+function %extractlane_4(i8x16) -> i8 {
+block0(v0: i8x16):
+    v1 = extractlane v0, 4
+    return v1
+}
+; run: %extractlane_4([1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16]) == 5
+
+function %extractlane_7(i16x8) -> i16 {
+block0(v0: i16x8):
+    v1 = extractlane v0, 7
+    return v1
+}
+; run: %extractlane_7([65528 65529 65530 65531 65532 65533 65534 65535]) == 65535
+
+function %extractlane_0(i32x4) -> i32 {
+block0(v0: i32x4):
+    v1 = extractlane v0, 0
+    return v1
+}
+; run: %extractlane_0([0 1 2 3]) == 0
+
+
+function %extractlane_1(i64x2) -> i64 {
+block0(v0: i64x2):
+    v1 = extractlane v0, 1
+    return v1
+}
+; run: %extractlane_1([0 4294967297]) == 4294967297

cranelift/filetests/filetests/runtests/simd-uaddsat-aarch64.clif

@@ -0,0 +1,20 @@
+test interpret
+test run
+target aarch64
+
+; i32x4 vectors aren't supported in `uadd_sat` outside AArch64 at the moment
+function %uaddsat_i32x4(i32x4, i32x4) -> i32x4 {
+block0(v0: i32x4, v1: i32x4):
+    v2 = uadd_sat v0, v1
+    return v2
+}
+; run: %uaddsat_i32x4([40 40 40 40], [2 2 2 2]) == [42 42 42 42]
+; run: %uaddsat_i32x4([4294967290 2147483640 4294967290 4294967290], [100 100 100 100]) == [4294967295 2147483740 4294967295 4294967295]
+
+function %uaddsat_i64x2(i64x2, i64x2) -> i64x2 {
+block0(v0: i64x2, v1: i64x2):
+    v2 = uadd_sat v0, v1
+    return v2
+}
+; run: %uaddsat_i64x2([40 40], [2 2]) == [42 42]
+; run: %uaddsat_i64x2([4294967290 18446744073709551610], [100 100]) == [4294967390 18446744073709551615]

cranelift/filetests/filetests/runtests/simd-uaddsat.clif

@@ -0,0 +1,19 @@
+test interpret
+test run
+target aarch64
+set enable_simd
+target x86_64
+
+function %uaddsat_i8x16(i8x16, i8x16) -> i8x16 {
+block0(v0: i8x16, v1: i8x16):
+    v2 = uadd_sat v0, v1
+    return v2
+}
+; run: %uaddsat_i8x16([150 150 150 150 150 150 150 150 150 150 150 150 150 150 150 150], [150 150 150 150 150 150 150 150 150 150 150 150 150 150 150 150]) == [255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255]
+
+function %uaddsat_i16x8(i16x8, i16x8) -> i16x8 {
+block0(v0: i16x8, v1: i16x8):
+    v2 = uadd_sat v0, v1
+    return v2
+}
+; run: %uaddsat_i16x8([65000 65000 65000 65000 65000 65000 65000 65000], [1000 1000 1000 1000 1000 1000 1000 1000]) == [65535 65535 65535 65535 65535 65535 65535 65535]

cranelift/filetests/filetests/runtests/simd-usubsat-aarch64.clif

@@ -0,0 +1,20 @@
+test interpret
+test run
+target aarch64
+
+; i32x4 vectors aren't supported in `usub_sat` outside AArch64 at the moment
+function %usubsat_i32x4(i32x4, i32x4) -> i32x4 {
+block0(v0: i32x4, v1: i32x4):
+    v2 = usub_sat v0, v1
+    return v2
+}
+; run: %usubsat_i32x4([40 40 40 40], [2 2 2 2]) == [38 38 38 38]
+; run: %usubsat_i32x4([4294967290 2147483640 4294967290 4294967290], [4294967295 4294967295 4294967295 4294967295]) == [0 0 0 0]
+
+function %usubsat_i64x2(i64x2, i64x2) -> i64x2 {
+block0(v0: i64x2, v1: i64x2):
+    v2 = usub_sat v0, v1
+    return v2
+}
+; run: %usubsat_i64x2([40 40], [2 2]) == [38 38]
+; run: %usubsat_i64x2([4294967290 2147483640], [4294967295 4294967295]) == [0 0]

cranelift/filetests/filetests/runtests/simd-usubsat.clif

@@ -0,0 +1,20 @@
+test interpret
+test run
+target aarch64
+set enable_simd
+target x86_64
+
+function %usubsat_i8x16(i8x16, i8x16) -> i8x16 {
+block0(v0: i8x16, v1: i8x16):
+    v2 = usub_sat v0, v1
+    return v2
+}
+; run: %usubsat_i8x16([150 150 150 150 150 150 150 150 150 150 150 150 150 150 150 150], [100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100]) == [50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50]
+; run: %usubsat_i8x16([150 150 150 150 150 150 150 150 150 150 150 150 150 150 150 150], [200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200]) == [0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0]
+
+function %usubsat_i16x8(i16x8, i16x8) -> i16x8 {
+block0(v0: i16x8, v1: i16x8):
+    v2 = usub_sat v0, v1
+    return v2
+}
+; run: %usubsat_i16x8([65534 65534 65534 65534 65534 65534 65534 65534], [65535 65535 65535 65535 65535 65535 65535 65535]) == [0 0 0 0 0 0 0 0]