Fix build after flake8 update.

There's a new version of flake8 out which doesn't like variables names
i, l, I.

No functional change intended.

lib/cretonne/meta/cdsl/settings.py

@@ -389,7 +389,7 @@ class Preset(object):
         The list will have an entry for each setting byte in the settings
         group.
         """
-        l = [(0, 0)] * self.group.settings_size
+        lst = [(0, 0)] * self.group.settings_size
 
         # Apply setting values in order.
         for s, v in self.values:
@@ -397,11 +397,11 @@ class Preset(object):
             s_mask = s.byte_mask()
             s_val = s.byte_for_value(v)
             assert (s_val & ~s_mask) == 0
-            l_mask, l_val = l[ofs]
+            l_mask, l_val = lst[ofs]
             # Accumulated mask of modified bits.
             l_mask |= s_mask
             # Overwrite the relevant bits with the new value.
             l_val = (l_val & ~s_mask) | s_val
-            l[ofs] = (l_mask, l_val)
+            lst[ofs] = (l_mask, l_val)
 
-        return l
+        return lst

lib/cretonne/meta/cdsl/test_ti.py

@@ -356,9 +356,9 @@ class TestRTL(TypeCheckingBaseTest):
             typing = ti_rtl(r, ti).extract()
 
             # The number of possible typings is 9 * (3+ 2*2 + 3) = 90
-            l = [(t[self.v0], t[self.v1]) for t in typing.concrete_typings()]
-            assert (len(l) == len(set(l)) and len(l) == 90)
-            for (tv0, tv1) in l:
+            lst = [(t[self.v0], t[self.v1]) for t in typing.concrete_typings()]
+            assert (len(lst) == len(set(lst)) and len(lst) == 90)
+            for (tv0, tv1) in lst:
                 typ0, typ1 = (tv0.singleton_type(), tv1.singleton_type())
                 if (op == ireduce):
                     assert typ0.wider_or_equal(typ1)
@@ -396,9 +396,9 @@ class TestRTL(TypeCheckingBaseTest):
             typing = ti_rtl(r, ti).extract()
 
             # The number of possible typings is 9*(2 + 1) = 27
-            l = [(t[self.v0], t[self.v1]) for t in typing.concrete_typings()]
-            assert (len(l) == len(set(l)) and len(l) == 27)
-            for (tv0, tv1) in l:
+            lst = [(t[self.v0], t[self.v1]) for t in typing.concrete_typings()]
+            assert (len(lst) == len(set(lst)) and len(lst) == 27)
+            for (tv0, tv1) in lst:
                 (typ0, typ1) = (tv0.singleton_type(), tv1.singleton_type())
                 if (op == fdemote):
                     assert typ0.wider_or_equal(typ1)

lib/cretonne/meta/isa/riscv/encodings.py

@@ -7,7 +7,7 @@ from base.immediates import intcc
 from .defs import RV32, RV64
 from .recipes import OPIMM, OPIMM32, OP, OP32, LUI, BRANCH, JALR, JAL
 from .recipes import LOAD, STORE
-from .recipes import R, Rshamt, Ricmp, I, Iz, Iicmp, Iret, Icall, Icopy
+from .recipes import R, Rshamt, Ricmp, Ii, Iz, Iicmp, Iret, Icall, Icopy
 from .recipes import U, UJ, UJcall, SB, SBzero, GPsp, GPfi, Irmov
 from .settings import use_m
 from cdsl.ast import Var
@@ -47,14 +47,14 @@ for inst,           inst_imm,      f3,    f7 in [
 
     # Immediate versions for add/xor/or/and.
     if inst_imm:
-        RV32.enc(inst_imm.i32, I, OPIMM(f3))
-        RV64.enc(inst_imm.i64, I, OPIMM(f3))
+        RV32.enc(inst_imm.i32, Ii, OPIMM(f3))
+        RV64.enc(inst_imm.i64, Ii, OPIMM(f3))
 
 # 32-bit ops in RV64.
 RV64.enc(base.iadd.i32, R, OP32(0b000, 0b0000000))
 RV64.enc(base.isub.i32, R, OP32(0b000, 0b0100000))
 # There are no andiw/oriw/xoriw variations.
-RV64.enc(base.iadd_imm.i32, I, OPIMM32(0b000))
+RV64.enc(base.iadd_imm.i32, Ii, OPIMM32(0b000))
 
 # Use iadd_imm with %x0 to materialize constants.
 RV32.enc(base.iconst.i32, Iz, OPIMM(0b000))

lib/cretonne/meta/isa/riscv/recipes.py

@@ -106,8 +106,8 @@ Ricmp = EncRecipe(
         'Ricmp', IntCompare, size=4, ins=(GPR, GPR), outs=GPR,
         emit='put_r(bits, in_reg0, in_reg1, out_reg0, sink);')
 
-I = EncRecipe(
-        'I', BinaryImm, size=4, ins=GPR, outs=GPR,
+Ii = EncRecipe(
+        'Ii', BinaryImm, size=4, ins=GPR, outs=GPR,
         instp=IsSignedInt(BinaryImm.imm, 12),
         emit='put_i(bits, in_reg0, imm.into(), out_reg0, sink);')
 

lib/cretonne/src/isa/riscv/mod.rs

@@ -147,7 +147,10 @@ mod tests {
         };
 
         // ADDI is I/0b00100
-        assert_eq!(encstr(&*isa, isa.encode(&dfg, &inst64, types::I64)), "I#04");
+        assert_eq!(
+            encstr(&*isa, isa.encode(&dfg, &inst64, types::I64)),
+            "Ii#04"
+        );
 
         // Try to encode iadd_imm.i64 v1, -10000.
         let inst64_large = InstructionData::BinaryImm {
@@ -167,7 +170,10 @@ mod tests {
         };
 
         // ADDIW is I/0b00110
-        assert_eq!(encstr(&*isa, isa.encode(&dfg, &inst32, types::I32)), "I#06");
+        assert_eq!(
+            encstr(&*isa, isa.encode(&dfg, &inst32, types::I32)),
+            "Ii#06"
+        );
     }
 
     // Same as above, but for RV32.
@@ -211,7 +217,10 @@ mod tests {
         };
 
         // ADDI is I/0b00100
-        assert_eq!(encstr(&*isa, isa.encode(&dfg, &inst32, types::I32)), "I#04");
+        assert_eq!(
+            encstr(&*isa, isa.encode(&dfg, &inst32, types::I32)),
+            "Ii#04"
+        );
 
         // Create an imul.i32 which is encodable in RV32, but only when use_m is true.
         let mul32 = InstructionData::Binary {