T0b1/wasmtime
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

s390x: Fix bitwise operations (#4146)

Browse Source 
Current codegen had a number of logic errors confusing
NAND with AND WITH COMPLEMENT, and NOR with OR WITH COMPLEMENT.

Add support for the missing z15 instructions and fix logic.
This commit is contained in:
Ulrich Weigand
2022-05-12 19:05:22 +02:00
committed by GitHub
parent 9538336f82
commit 0243a16679
7 changed files with 151 additions and 75 deletions
Download Patch File Download Diff File Expand all files Collapse all files

24
cranelift/filetests/filetests/isa/s390x/bitwise-arch13.clif
View File

@@ -13,7 +13,7 @@ block0(v0: i64, v1: i64):
}
; block0:
; nngrk %r2, %r2, %r3
; ncgrk %r2, %r2, %r3
; br %r14
function %band_not_i32(i32, i32) -> i32 {
@@ -23,7 +23,7 @@ block0(v0: i32, v1: i32):
}
; block0:
; nnrk %r2, %r2, %r3
; ncrk %r2, %r2, %r3
; br %r14
function %band_not_i16(i16, i16) -> i16 {
@@ -33,7 +33,7 @@ block0(v0: i16, v1: i16):
}
; block0:
; nnrk %r2, %r2, %r3
; ncrk %r2, %r2, %r3
; br %r14
function %band_not_i8(i8, i8) -> i8 {
@@ -43,7 +43,7 @@ block0(v0: i8, v1: i8):
}
; block0:
; nnrk %r2, %r2, %r3
; ncrk %r2, %r2, %r3
; br %r14
function %bor_not_i64(i64, i64) -> i64 {
@@ -53,7 +53,7 @@ block0(v0: i64, v1: i64):
}
; block0:
; nogrk %r2, %r2, %r3
; ocgrk %r2, %r2, %r3
; br %r14
function %bor_not_i32(i32, i32) -> i32 {
@@ -63,7 +63,7 @@ block0(v0: i32, v1: i32):
}
; block0:
; nork %r2, %r2, %r3
; ocrk %r2, %r2, %r3
; br %r14
function %bor_not_i16(i16, i16) -> i16 {
@@ -73,7 +73,7 @@ block0(v0: i16, v1: i16):
}
; block0:
; nork %r2, %r2, %r3
; ocrk %r2, %r2, %r3
; br %r14
function %bor_not_i8(i8, i8) -> i8 {
@@ -83,7 +83,7 @@ block0(v0: i8, v1: i8):
}
; block0:
; nork %r2, %r2, %r3
; ocrk %r2, %r2, %r3
; br %r14
function %bxor_not_i64(i64, i64) -> i64 {
@@ -174,7 +174,7 @@ block0(v0: i64, v1: i64, v2: i64):
; block0:
; ngrk %r5, %r3, %r2
; nngrk %r3, %r4, %r2
; ncgrk %r3, %r4, %r2
; ogrk %r2, %r3, %r5
; br %r14
@@ -186,7 +186,7 @@ block0(v0: i32, v1: i32, v2: i32):
; block0:
; nrk %r5, %r3, %r2
; nnrk %r3, %r4, %r2
; ncrk %r3, %r4, %r2
; ork %r2, %r3, %r5
; br %r14
@@ -198,7 +198,7 @@ block0(v0: i16, v1: i16, v2: i16):
; block0:
; nrk %r5, %r3, %r2
; nnrk %r3, %r4, %r2
; ncrk %r3, %r4, %r2
; ork %r2, %r3, %r5
; br %r14
@@ -210,7 +210,7 @@ block0(v0: i8, v1: i8, v2: i8):
; block0:
; nrk %r5, %r3, %r2
; nnrk %r3, %r4, %r2
; ncrk %r3, %r4, %r2
; ork %r2, %r3, %r5
; br %r14

46
cranelift/filetests/filetests/isa/s390x/bitwise.clif
View File

@@ -306,9 +306,9 @@ block0(v0: i64, v1: i64):
}
; block0:
; xilf %r3, 4294967295
; xihf %r3, 4294967295
; ngr %r2, %r3
; xilf %r2, 4294967295
; xihf %r2, 4294967295
; br %r14
function %band_not_i32(i32, i32) -> i32 {
@@ -318,8 +318,8 @@ block0(v0: i32, v1: i32):
}
; block0:
; xilf %r3, 4294967295
; nr %r2, %r3
; xilf %r2, 4294967295
; br %r14
function %band_not_i16(i16, i16) -> i16 {
@@ -329,8 +329,8 @@ block0(v0: i16, v1: i16):
}
; block0:
; xilf %r3, 4294967295
; nr %r2, %r3
; xilf %r2, 4294967295
; br %r14
function %band_not_i8(i8, i8) -> i8 {
@@ -340,8 +340,8 @@ block0(v0: i8, v1: i8):
}
; block0:
; xilf %r3, 4294967295
; nr %r2, %r3
; xilf %r2, 4294967295
; br %r14
function %bor_not_i64(i64, i64) -> i64 {
@@ -351,9 +351,9 @@ block0(v0: i64, v1: i64):
}
; block0:
; xilf %r3, 4294967295
; xihf %r3, 4294967295
; ogr %r2, %r3
; xilf %r2, 4294967295
; xihf %r2, 4294967295
; br %r14
function %bor_not_i32(i32, i32) -> i32 {
@@ -363,8 +363,8 @@ block0(v0: i32, v1: i32):
}
; block0:
; xilf %r3, 4294967295
; or %r2, %r3
; xilf %r2, 4294967295
; br %r14
function %bor_not_i16(i16, i16) -> i16 {
@@ -374,8 +374,8 @@ block0(v0: i16, v1: i16):
}
; block0:
; xilf %r3, 4294967295
; or %r2, %r3
; xilf %r2, 4294967295
; br %r14
function %bor_not_i8(i8, i8) -> i8 {
@@ -385,8 +385,8 @@ block0(v0: i8, v1: i8):
}
; block0:
; xilf %r3, 4294967295
; or %r2, %r3
; xilf %r2, 4294967295
; br %r14
function %bxor_not_i64(i64, i64) -> i64 {
@@ -483,10 +483,10 @@ block0(v0: i64, v1: i64, v2: i64):
; block0:
; ngrk %r5, %r3, %r2
; ngrk %r3, %r4, %r2
; xilf %r3, 4294967295
; xihf %r3, 4294967295
; ogrk %r2, %r3, %r5
; xilf %r2, 4294967295
; xihf %r2, 4294967295
; ngrk %r2, %r4, %r2
; ogr %r2, %r5
; br %r14
function %bitselect_i32(i32, i32, i32) -> i32 {
@@ -497,9 +497,9 @@ block0(v0: i32, v1: i32, v2: i32):
; block0:
; nrk %r5, %r3, %r2
; nrk %r3, %r4, %r2
; xilf %r3, 4294967295
; ork %r2, %r3, %r5
; xilf %r2, 4294967295
; nrk %r2, %r4, %r2
; or %r2, %r5
; br %r14
function %bitselect_i16(i16, i16, i16) -> i16 {
@@ -510,9 +510,9 @@ block0(v0: i16, v1: i16, v2: i16):
; block0:
; nrk %r5, %r3, %r2
; nrk %r3, %r4, %r2
; xilf %r3, 4294967295
; ork %r2, %r3, %r5
; xilf %r2, 4294967295
; nrk %r2, %r4, %r2
; or %r2, %r5
; br %r14
function %bitselect_i8(i8, i8, i8) -> i8 {
@@ -523,8 +523,8 @@ block0(v0: i8, v1: i8, v2: i8):
; block0:
; nrk %r5, %r3, %r2
; nrk %r3, %r4, %r2
; xilf %r3, 4294967295
; ork %r2, %r3, %r5
; xilf %r2, 4294967295
; nrk %r2, %r4, %r2
; or %r2, %r5
; br %r14