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s390x: Fix bitwise operations (#4146)

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Current codegen had a number of logic errors confusing
NAND with AND WITH COMPLEMENT, and NOR with OR WITH COMPLEMENT.

Add support for the missing z15 instructions and fix logic.
This commit is contained in:
Ulrich Weigand
2022-05-12 19:05:22 +02:00
committed by GitHub
parent 9538336f82
commit 0243a16679
7 changed files with 151 additions and 75 deletions
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20
cranelift/codegen/src/isa/s390x/inst/mod.rs
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@@ -193,9 +193,11 @@ impl Inst {
// These depend on the opcode
Inst::AluRRR { alu_op, .. } => match alu_op {
ALUOp::NotAnd32 | ALUOp::NotAnd64 => InstructionSet::MIE2,
ALUOp::NotOrr32 | ALUOp::NotOrr64 => InstructionSet::MIE2,
ALUOp::NotXor32 | ALUOp::NotXor64 => InstructionSet::MIE2,
ALUOp::AndNot32 | ALUOp::AndNot64 => InstructionSet::MIE2,
ALUOp::OrrNot32 | ALUOp::OrrNot64 => InstructionSet::MIE2,
ALUOp::XorNot32 | ALUOp::XorNot64 => InstructionSet::MIE2,
_ => InstructionSet::Base,
},
Inst::UnaryRR { op, .. } => match op {
@@ -933,12 +935,16 @@ impl Inst {
ALUOp::Orr64 => ("ogrk", true),
ALUOp::Xor32 => ("xrk", true),
ALUOp::Xor64 => ("xgrk", true),
ALUOp::AndNot32 => ("nnrk", false),
ALUOp::AndNot64 => ("nngrk", false),
ALUOp::OrrNot32 => ("nork", false),
ALUOp::OrrNot64 => ("nogrk", false),
ALUOp::XorNot32 => ("nxrk", false),
ALUOp::XorNot64 => ("nxgrk", false),
ALUOp::NotAnd32 => ("nnrk", false),
ALUOp::NotAnd64 => ("nngrk", false),
ALUOp::NotOrr32 => ("nork", false),
ALUOp::NotOrr64 => ("nogrk", false),
ALUOp::NotXor32 => ("nxrk", false),
ALUOp::NotXor64 => ("nxgrk", false),
ALUOp::AndNot32 => ("ncrk", false),
ALUOp::AndNot64 => ("ncgrk", false),
ALUOp::OrrNot32 => ("ocrk", false),
ALUOp::OrrNot64 => ("ocgrk", false),
_ => unreachable!(),
};
if have_rr && rd.to_reg() == rn {