Intel encodings for fadd, fsub, fmul, fdiv.

filetests/isa/intel/binary32-float.cton

@@ -17,6 +17,28 @@ ebb0:
     ; asm: cvtsi2ss %esi, %xmm2
     [-,%xmm2]           v11 = fcvt_from_sint.f32 v1             ; bin: f3 0f 2a d6
 
+    ; Binary arithmetic.
+
+    ; asm: addss %xmm2, %xmm5
+    [-,%xmm5]           v20 = fadd v10, v11                     ; bin: f3 0f 58 ea
+    ; asm: addss %xmm5, %xmm2
+    [-,%xmm2]           v21 = fadd v11, v10                     ; bin: f3 0f 58 d5 
+
+    ; asm: subss %xmm2, %xmm5
+    [-,%xmm5]           v22 = fsub v10, v11                     ; bin: f3 0f 5c ea
+    ; asm: subss %xmm5, %xmm2
+    [-,%xmm2]           v23 = fsub v11, v10                     ; bin: f3 0f 5c d5
+
+    ; asm: mulss %xmm2, %xmm5
+    [-,%xmm5]           v24 = fmul v10, v11                     ; bin: f3 0f 59 ea
+    ; asm: mulss %xmm5, %xmm2
+    [-,%xmm2]           v25 = fmul v11, v10                     ; bin: f3 0f 59 d5
+
+    ; asm: divss %xmm2, %xmm5
+    [-,%xmm5]           v26 = fdiv v10, v11                     ; bin: f3 0f 5e ea
+    ; asm: divss %xmm5, %xmm2
+    [-,%xmm2]           v27 = fdiv v11, v10                     ; bin: f3 0f 5e d5
+
     return
 }
 
@@ -25,10 +47,32 @@ ebb0:
     [-,%rcx]            v0 = iconst.i32 1
     [-,%rsi]            v1 = iconst.i32 2
 
+    ; Binary arithmetic.
+
     ; asm: cvtsi2sd %ecx, %xmm5
     [-,%xmm5]           v10 = fcvt_from_sint.f64 v0             ; bin: f2 0f 2a e9
     ; asm: cvtsi2sd %esi, %xmm2
     [-,%xmm2]           v11 = fcvt_from_sint.f64 v1             ; bin: f2 0f 2a d6
 
+    ; asm: addsd %xmm2, %xmm5
+    [-,%xmm5]           v20 = fadd v10, v11                     ; bin: f2 0f 58 ea
+    ; asm: addsd %xmm5, %xmm2
+    [-,%xmm2]           v21 = fadd v11, v10                     ; bin: f2 0f 58 d5 
+
+    ; asm: subsd %xmm2, %xmm5
+    [-,%xmm5]           v22 = fsub v10, v11                     ; bin: f2 0f 5c ea
+    ; asm: subsd %xmm5, %xmm2
+    [-,%xmm2]           v23 = fsub v11, v10                     ; bin: f2 0f 5c d5
+
+    ; asm: mulsd %xmm2, %xmm5
+    [-,%xmm5]           v24 = fmul v10, v11                     ; bin: f2 0f 59 ea
+    ; asm: mulsd %xmm5, %xmm2
+    [-,%xmm2]           v25 = fmul v11, v10                     ; bin: f2 0f 59 d5
+
+    ; asm: divsd %xmm2, %xmm5
+    [-,%xmm5]           v26 = fdiv v10, v11                     ; bin: f2 0f 5e ea
+    ; asm: divsd %xmm5, %xmm2
+    [-,%xmm2]           v27 = fdiv v11, v10                     ; bin: f2 0f 5e d5
+
     return
 }

filetests/isa/intel/binary64-float.cton

@@ -25,6 +25,28 @@ ebb0:
     ; asm: cvtsi2ssq %r14, %xmm10
     [-,%xmm10]          v13 = fcvt_from_sint.f32 v3             ; TODO: f3 4d 0f 2a d6
 
+    ; Binary arithmetic.
+
+    ; asm: addss %xmm10, %xmm5
+    [-,%xmm5]           v20 = fadd v10, v11                     ; bin: f3 41 0f 58 ea
+    ; asm: addss %xmm5, %xmm10
+    [-,%xmm10]           v21 = fadd v11, v10                    ; bin: f3 44 0f 58 d5 
+
+    ; asm: subss %xmm10, %xmm5
+    [-,%xmm5]           v22 = fsub v10, v11                     ; bin: f3 41 0f 5c ea
+    ; asm: subss %xmm5, %xmm10
+    [-,%xmm10]           v23 = fsub v11, v10                    ; bin: f3 44 0f 5c d5
+
+    ; asm: mulss %xmm10, %xmm5
+    [-,%xmm5]           v24 = fmul v10, v11                     ; bin: f3 41 0f 59 ea
+    ; asm: mulss %xmm5, %xmm10
+    [-,%xmm10]           v25 = fmul v11, v10                    ; bin: f3 44 0f 59 d5
+
+    ; asm: divss %xmm10, %xmm5
+    [-,%xmm5]           v26 = fdiv v10, v11                     ; bin: f3 41 0f 5e ea
+    ; asm: divss %xmm5, %xmm10
+    [-,%xmm10]           v27 = fdiv v11, v10                    ; bin: f3 44 0f 5e d5
+
     return
 }
 
@@ -45,5 +67,27 @@ ebb0:
     ; asm: cvtsi2sdq %r14, %xmm10
     [-,%xmm10]          v13 = fcvt_from_sint.f64 v3             ; TODO: f2 4d 0f 2a d6
 
+    ; Binary arithmetic.
+
+    ; asm: addsd %xmm10, %xmm5
+    [-,%xmm5]           v20 = fadd v10, v11                     ; bin: f2 41 0f 58 ea
+    ; asm: addsd %xmm5, %xmm10
+    [-,%xmm10]           v21 = fadd v11, v10                    ; bin: f2 44 0f 58 d5 
+
+    ; asm: subsd %xmm10, %xmm5
+    [-,%xmm5]           v22 = fsub v10, v11                     ; bin: f2 41 0f 5c ea
+    ; asm: subsd %xmm5, %xmm10
+    [-,%xmm10]           v23 = fsub v11, v10                    ; bin: f2 44 0f 5c d5
+
+    ; asm: mulsd %xmm10, %xmm5
+    [-,%xmm5]           v24 = fmul v10, v11                     ; bin: f2 41 0f 59 ea
+    ; asm: mulsd %xmm5, %xmm10
+    [-,%xmm10]           v25 = fmul v11, v10                    ; bin: f2 44 0f 59 d5
+
+    ; asm: divsd %xmm10, %xmm5
+    [-,%xmm5]           v26 = fdiv v10, v11                     ; bin: f2 41 0f 5e ea
+    ; asm: divsd %xmm5, %xmm10
+    [-,%xmm10]           v27 = fdiv v11, v10                    ; bin: f2 44 0f 5e d5
+
     return
 }

filetests/wasm/f32-arith.cton

@@ -0,0 +1,52 @@
+; Test basic code generation for f32 arithmetic WebAssembly instructions.
+test compile
+
+set is_64bit=0
+isa intel haswell
+
+set is_64bit=1
+isa intel haswell
+
+; Constants.
+
+; function %f32_const() -> f32
+
+; Unary operations
+
+; function %f32_abs(f32) -> f32
+; function %f32_neg(f32) -> f32
+; function %f32_sqrt(f32) -> f32
+; function %f32_ceil(f32) -> f32
+; function %f32_floor(f32) -> f32
+; function %f32_trunc(f32) -> f32
+; function %f32_nearest (f32) -> f32
+
+; Binary Operations
+
+function %f32_add(f32, f32) -> f32 {
+ebb0(v0: f32, v1: f32):
+    v2 = fadd v0, v1
+    return v2
+}
+
+function %f32_sub(f32, f32) -> f32 {
+ebb0(v0: f32, v1: f32):
+    v2 = fsub v0, v1
+    return v2
+}
+
+function %f32_mul(f32, f32) -> f32 {
+ebb0(v0: f32, v1: f32):
+    v2 = fmul v0, v1
+    return v2
+}
+
+function %f32_div(f32, f32) -> f32 {
+ebb0(v0: f32, v1: f32):
+    v2 = fdiv v0, v1
+    return v2
+}
+
+; function %f32_min(f32, f32) -> f32
+; function %f32_max(f32, f32) -> f32
+; function %f32_copysign(f32, f32) -> f32

filetests/wasm/f64-arith.cton

@@ -0,0 +1,52 @@
+; Test basic code generation for f64 arithmetic WebAssembly instructions.
+test compile
+
+set is_64bit=0
+isa intel haswell
+
+set is_64bit=1
+isa intel haswell
+
+; Constants.
+
+; function %f64_const() -> f64
+
+; Unary operations
+
+; function %f64_abs(f64) -> f64
+; function %f64_neg(f64) -> f64
+; function %f64_sqrt(f64) -> f64
+; function %f64_ceil(f64) -> f64
+; function %f64_floor(f64) -> f64
+; function %f64_trunc(f64) -> f64
+; function %f64_nearest (f64) -> f64
+
+; Binary Operations
+
+function %f64_add(f64, f64) -> f64 {
+ebb0(v0: f64, v1: f64):
+    v2 = fadd v0, v1
+    return v2
+}
+
+function %f64_sub(f64, f64) -> f64 {
+ebb0(v0: f64, v1: f64):
+    v2 = fsub v0, v1
+    return v2
+}
+
+function %f64_mul(f64, f64) -> f64 {
+ebb0(v0: f64, v1: f64):
+    v2 = fmul v0, v1
+    return v2
+}
+
+function %f64_div(f64, f64) -> f64 {
+ebb0(v0: f64, v1: f64):
+    v2 = fdiv v0, v1
+    return v2
+}
+
+; function %f64_min(f64, f64) -> f64
+; function %f64_max(f64, f64) -> f64
+; function %f64_copysign(f64, f64) -> f64

lib/cretonne/meta/isa/intel/encodings.py

@@ -222,3 +222,17 @@ I64.enc(base.fcvt_from_sint.f32.i32, *r.furm(0xf3, 0x0f, 0x2A))
 I32.enc(base.fcvt_from_sint.f64.i32, *r.furm(0xf2, 0x0f, 0x2A))
 I64.enc(base.fcvt_from_sint.f64.i32, *r.furm.rex(0xf2, 0x0f, 0x2A))
 I64.enc(base.fcvt_from_sint.f64.i32, *r.furm(0xf2, 0x0f, 0x2A))
+
+# Binary arithmetic ops.
+for inst, opc in [
+        (base.fadd, 0x58),
+        (base.fsub, 0x5c),
+        (base.fmul, 0x59),
+        (base.fdiv, 0x5e)]:
+    I32.enc(inst.f32, *r.frm(0xf3, 0x0f, opc))
+    I64.enc(inst.f32, *r.frm.rex(0xf3, 0x0f, opc))
+    I64.enc(inst.f32, *r.frm(0xf3, 0x0f, opc))
+
+    I32.enc(inst.f64, *r.frm(0xf2, 0x0f, opc))
+    I64.enc(inst.f64, *r.frm.rex(0xf2, 0x0f, opc))
+    I64.enc(inst.f64, *r.frm(0xf2, 0x0f, opc))

lib/cretonne/meta/isa/intel/recipes.py

@@ -197,7 +197,7 @@ null = EncRecipe('null', Unary, size=0, ins=GPR, outs=0, emit='')
 # XX opcode, no ModR/M.
 noop = TailRecipe(
         'noop', Nullary, size=0, ins=(), outs=(),
-        emit='PUT_OP(bits, 0, sink);')
+        emit='PUT_OP(bits, BASE_REX, sink);')
 
 # XX /r
 rr = TailRecipe(
@@ -215,6 +215,14 @@ rrx = TailRecipe(
         modrm_rr(in_reg1, in_reg0, sink);
         ''')
 
+# XX /r with FPR ins and outs. RM form.
+frm = TailRecipe(
+        'frr', Binary, size=1, ins=(FPR, FPR), outs=0,
+        emit='''
+        PUT_OP(bits, rex2(in_reg1, in_reg0), sink);
+        modrm_rr(in_reg1, in_reg0, sink);
+        ''')
+
 # XX /r, but for a unary operator with separate input/output register, like
 # copies. MR form.
 umr = TailRecipe(