Intel encodings for fadd, fsub, fmul, fdiv.

lib/cretonne/meta/isa/intel/encodings.py

@@ -222,3 +222,17 @@ I64.enc(base.fcvt_from_sint.f32.i32, *r.furm(0xf3, 0x0f, 0x2A))
 I32.enc(base.fcvt_from_sint.f64.i32, *r.furm(0xf2, 0x0f, 0x2A))
 I64.enc(base.fcvt_from_sint.f64.i32, *r.furm.rex(0xf2, 0x0f, 0x2A))
 I64.enc(base.fcvt_from_sint.f64.i32, *r.furm(0xf2, 0x0f, 0x2A))
+
+# Binary arithmetic ops.
+for inst, opc in [
+        (base.fadd, 0x58),
+        (base.fsub, 0x5c),
+        (base.fmul, 0x59),
+        (base.fdiv, 0x5e)]:
+    I32.enc(inst.f32, *r.frm(0xf3, 0x0f, opc))
+    I64.enc(inst.f32, *r.frm.rex(0xf3, 0x0f, opc))
+    I64.enc(inst.f32, *r.frm(0xf3, 0x0f, opc))
+
+    I32.enc(inst.f64, *r.frm(0xf2, 0x0f, opc))
+    I64.enc(inst.f64, *r.frm.rex(0xf2, 0x0f, opc))
+    I64.enc(inst.f64, *r.frm(0xf2, 0x0f, opc))

lib/cretonne/meta/isa/intel/recipes.py

@@ -197,7 +197,7 @@ null = EncRecipe('null', Unary, size=0, ins=GPR, outs=0, emit='')
 # XX opcode, no ModR/M.
 noop = TailRecipe(
         'noop', Nullary, size=0, ins=(), outs=(),
-        emit='PUT_OP(bits, 0, sink);')
+        emit='PUT_OP(bits, BASE_REX, sink);')
 
 # XX /r
 rr = TailRecipe(
@@ -215,6 +215,14 @@ rrx = TailRecipe(
         modrm_rr(in_reg1, in_reg0, sink);
         ''')
 
+# XX /r with FPR ins and outs. RM form.
+frm = TailRecipe(
+        'frr', Binary, size=1, ins=(FPR, FPR), outs=0,
+        emit='''
+        PUT_OP(bits, rex2(in_reg1, in_reg0), sink);
+        modrm_rr(in_reg1, in_reg0, sink);
+        ''')
+
 # XX /r, but for a unary operator with separate input/output register, like
 # copies. MR form.
 umr = TailRecipe(