4abad24610
This is realized by two changes: first, GP and vector operand size are completely separated using one extra bit. If the operand size of an instruction is derived from VEX.L (or EVEX.L'L), then the "opsize" bits indicate how to derive a smaller vector size (half/quarter/eighth).
597 lines
20 KiB
C
597 lines
20 KiB
C
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#include <stdbool.h>
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#include <stddef.h>
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#include <stdint.h>
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#include <fadec.h>
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#ifdef __GNUC__
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#define LIKELY(x) __builtin_expect((x), 1)
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#define UNLIKELY(x) __builtin_expect((x), 0)
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#else
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#define LIKELY(x) (x)
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#define UNLIKELY(x) (x)
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#endif
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// Defines FD_TABLE_OFFSET_32 and FD_TABLE_OFFSET_64, if available
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#define FD_DECODE_TABLE_DEFINES
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#include <fadec-decode-private.inc>
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#undef FD_DECODE_TABLE_DEFINES
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enum DecodeMode {
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DECODE_64 = 0,
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DECODE_32 = 1,
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};
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typedef enum DecodeMode DecodeMode;
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#define ENTRY_NONE 0
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#define ENTRY_INSTR 1
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#define ENTRY_TABLE256 2
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#define ENTRY_TABLE16 3
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#define ENTRY_TABLE8E 4
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#define ENTRY_TABLE_PREFIX 5
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#define ENTRY_TABLE_VEX 6
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#define ENTRY_TABLE_ROOT 8
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#define ENTRY_MASK 7
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static unsigned
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table_walk(unsigned cur_idx, unsigned entry_idx, unsigned* out_kind) {
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static _Alignas(16) const uint16_t _decode_table[] = {
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#define FD_DECODE_TABLE_DATA
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#include <fadec-decode-private.inc>
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#undef FD_DECODE_TABLE_DATA
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};
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unsigned entry = _decode_table[cur_idx + entry_idx];
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*out_kind = entry & ENTRY_MASK;
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return (entry & ~ENTRY_MASK) >> 1;
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}
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#define LOAD_LE_1(buf) ((uint64_t) *(uint8_t*) (buf))
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#define LOAD_LE_2(buf) (LOAD_LE_1(buf) | LOAD_LE_1((uint8_t*) (buf) + 1)<<8)
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#define LOAD_LE_3(buf) (LOAD_LE_2(buf) | LOAD_LE_1((uint8_t*) (buf) + 2)<<16)
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#define LOAD_LE_4(buf) (LOAD_LE_2(buf) | LOAD_LE_2((uint8_t*) (buf) + 2)<<16)
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#define LOAD_LE_8(buf) (LOAD_LE_4(buf) | LOAD_LE_4((uint8_t*) (buf) + 4)<<32)
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enum
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{
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PREFIX_REXB = 0x01,
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PREFIX_REXX = 0x02,
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PREFIX_REXR = 0x04,
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PREFIX_REXW = 0x08,
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PREFIX_REX = 0x40,
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PREFIX_VEXL = 0x10,
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};
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struct InstrDesc
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{
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uint16_t type;
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uint16_t operand_indices;
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uint16_t operand_sizes;
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uint16_t reg_types;
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};
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#define DESC_HAS_MODRM(desc) (((desc)->operand_indices & (3 << 0)) != 0)
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#define DESC_MODRM_IDX(desc) ((((desc)->operand_indices >> 0) & 3) ^ 3)
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#define DESC_HAS_MODREG(desc) (((desc)->operand_indices & (3 << 2)) != 0)
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#define DESC_MODREG_IDX(desc) ((((desc)->operand_indices >> 2) & 3) ^ 3)
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#define DESC_HAS_VEXREG(desc) (((desc)->operand_indices & (3 << 4)) != 0)
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#define DESC_VEXREG_IDX(desc) ((((desc)->operand_indices >> 4) & 3) ^ 3)
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#define DESC_IMM_CONTROL(desc) (((desc)->operand_indices >> 12) & 0x7)
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#define DESC_IMM_IDX(desc) ((((desc)->operand_indices >> 6) & 3) ^ 3)
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#define DESC_ZEROREG_VAL(desc) (((desc)->operand_indices >> 10) & 1)
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#define DESC_LOCK(desc) (((desc)->operand_indices >> 11) & 1)
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#define DESC_VSIB(desc) (((desc)->operand_indices >> 15) & 1)
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#define DESC_OPSIZE(desc) (((desc)->reg_types >> 11) & 7)
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#define DESC_SIZE_FIX1(desc) (((desc)->operand_sizes >> 10) & 7)
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#define DESC_SIZE_FIX2(desc) (((desc)->operand_sizes >> 13) & 3)
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#define DESC_INSTR_WIDTH(desc) (((desc)->operand_sizes >> 15) & 1)
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#define DESC_MODRM(desc) (((desc)->reg_types >> 14) & 1)
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#define DESC_IGN66(desc) (((desc)->reg_types >> 15) & 1)
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#define DESC_REGTY_MODRM(desc) (((desc)->reg_types >> 0) & 7)
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#define DESC_REGTY_MODREG(desc) (((desc)->reg_types >> 3) & 7)
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#define DESC_REGTY_VEXREG(desc) (((desc)->reg_types >> 6) & 3)
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int
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fd_decode(const uint8_t* buffer, size_t len_sz, int mode_int, uintptr_t address,
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FdInstr* instr)
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{
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int len = len_sz > 15 ? 15 : len_sz;
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// Ensure that we can actually handle the decode request
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DecodeMode mode;
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unsigned table_idx;
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unsigned kind = ENTRY_TABLE_ROOT;
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switch (mode_int)
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{
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#if defined(FD_TABLE_OFFSET_32)
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case 32: table_idx = FD_TABLE_OFFSET_32; mode = DECODE_32; break;
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#endif
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#if defined(FD_TABLE_OFFSET_64)
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case 64: table_idx = FD_TABLE_OFFSET_64; mode = DECODE_64; break;
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#endif
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default: return FD_ERR_INTERNAL;
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}
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int off = 0;
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uint8_t vex_operand = 0;
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unsigned prefix_rep = 0;
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bool prefix_lock = false;
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bool prefix_66 = false;
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uint8_t addr_size = mode == DECODE_64 ? 3 : 2;
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unsigned prefix_rex = 0;
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int rex_off = -1;
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instr->segment = FD_REG_NONE;
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if (mode == DECODE_32) {
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while (LIKELY(off < len))
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{
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uint8_t prefix = buffer[off];
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switch (UNLIKELY(prefix))
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{
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default: goto prefix_end;
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// From segment overrides, the last one wins.
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case 0x26: instr->segment = FD_REG_ES; break;
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case 0x2e: instr->segment = FD_REG_CS; break;
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case 0x36: instr->segment = FD_REG_SS; break;
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case 0x3e: instr->segment = FD_REG_DS; break;
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case 0x64: instr->segment = FD_REG_FS; break;
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case 0x65: instr->segment = FD_REG_GS; break;
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case 0x66: prefix_66 = true; break;
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case 0x67: addr_size = 1; break;
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case 0xf0: prefix_lock = true; break;
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case 0xf3: prefix_rep = 2; break;
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case 0xf2: prefix_rep = 3; break;
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}
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off++;
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}
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}
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if (mode == DECODE_64) {
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while (LIKELY(off < len))
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{
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uint8_t prefix = buffer[off];
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switch (UNLIKELY(prefix))
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{
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default: goto prefix_end;
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// ES/CS/SS/DS overrides are ignored.
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case 0x26: case 0x2e: case 0x36: case 0x3e: break;
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// From segment overrides, the last one wins.
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case 0x64: instr->segment = FD_REG_FS; break;
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case 0x65: instr->segment = FD_REG_GS; break;
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case 0x66: prefix_66 = true; break;
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case 0x67: addr_size = 2; break;
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case 0xf0: prefix_lock = true; break;
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case 0xf3: prefix_rep = 2; break;
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case 0xf2: prefix_rep = 3; break;
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case 0x40: case 0x41: case 0x42: case 0x43: case 0x44: case 0x45:
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case 0x46: case 0x47: case 0x48: case 0x49: case 0x4a: case 0x4b:
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case 0x4c: case 0x4d: case 0x4e: case 0x4f:
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prefix_rex = prefix;
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rex_off = off;
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break;
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}
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off++;
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}
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}
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prefix_end:
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// REX prefix is only considered if it is the last prefix.
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if (rex_off != off - 1)
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prefix_rex = 0;
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if (UNLIKELY(off >= len))
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return FD_ERR_PARTIAL;
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unsigned opcode_escape = 0;
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if (buffer[off] == 0x0f)
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{
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if (UNLIKELY(off + 1 >= len))
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return FD_ERR_PARTIAL;
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if (buffer[off + 1] == 0x38)
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opcode_escape = 2;
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else if (buffer[off + 1] == 0x3a)
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opcode_escape = 3;
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else
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opcode_escape = 1;
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off += opcode_escape >= 2 ? 2 : 1;
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}
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else if (UNLIKELY((buffer[off] & 0xfe) == 0xc4)) // VEX c4/c5
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{
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if (UNLIKELY(off + 1 >= len))
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return FD_ERR_PARTIAL;
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if (mode == DECODE_32 && (buffer[off + 1] & 0xc0) != 0xc0)
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goto skipvex;
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// VEX + 66/F3/F2/REX will #UD.
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// Note: REX is also here only respected if it immediately precedes the
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// opcode, in this case the VEX "prefix".
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if (prefix_66 || prefix_rep || prefix_rex)
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return FD_ERR_UD;
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uint8_t byte = buffer[off + 1];
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prefix_rex |= byte & 0x80 ? 0 : PREFIX_REXR;
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if (buffer[off] == 0xc4) // 3-byte VEX
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{
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prefix_rex |= byte & 0x40 ? 0 : PREFIX_REXX;
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// SDM Vol 2A 2-15 (Dec. 2016): Ignored in 32-bit mode
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prefix_rex |= mode != DECODE_64 || (byte & 0x20) ? 0 : PREFIX_REXB;
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if (byte & 0x1c) // Bits 4:2 of opcode_escape must be clear.
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return FD_ERR_UD;
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opcode_escape = (byte & 0x03) | 4; // 4 is table index with VEX
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// Load third byte of VEX prefix
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if (UNLIKELY(off + 2 >= len))
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return FD_ERR_PARTIAL;
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byte = buffer[off + 2];
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prefix_rex |= byte & 0x80 ? PREFIX_REXW : 0;
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}
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else // 2-byte VEX
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opcode_escape = 1 | 4; // 4 is table index with VEX, 0f escape
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prefix_rex |= byte & 0x04 ? PREFIX_VEXL : 0;
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prefix_rep = (byte & 2) ? (byte & 3) : 0;
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prefix_66 = (byte & 3) == 1;
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vex_operand = ((byte & 0x78) >> 3) ^ 0xf;
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off += buffer[off] == 0xc4 ? 3 : 2;
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skipvex:;
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}
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table_idx = table_walk(table_idx, opcode_escape, &kind);
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if (kind == ENTRY_TABLE256 && LIKELY(off < len))
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table_idx = table_walk(table_idx, buffer[off++], &kind);
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// Handle mandatory prefixes (which behave like an opcode ext.).
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if (kind == ENTRY_TABLE_PREFIX)
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{
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// If there is no REP/REPNZ prefix offer 66h as mandatory prefix. If
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// there is a REP prefix, then the 66h prefix is ignored here.
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uint8_t mandatory_prefix = prefix_rep ? prefix_rep : !!prefix_66;
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table_idx = table_walk(table_idx, mandatory_prefix, &kind);
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}
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// Then, walk through ModR/M-encoded opcode extensions.
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if (kind == ENTRY_TABLE16 && LIKELY(off < len)) {
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unsigned isreg = (buffer[off] & 0xc0) == 0xc0 ? 8 : 0;
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table_idx = table_walk(table_idx, ((buffer[off] >> 3) & 7) | isreg, &kind);
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if (kind == ENTRY_TABLE8E)
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table_idx = table_walk(table_idx, buffer[off] & 7, &kind);
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}
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// For VEX prefix, we have to distinguish between VEX.W and VEX.L which may
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// be part of the opcode.
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if (UNLIKELY(kind == ENTRY_TABLE_VEX))
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{
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uint8_t index = 0;
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index |= prefix_rex & PREFIX_REXW ? (1 << 0) : 0;
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index |= prefix_rex & PREFIX_VEXL ? (1 << 1) : 0;
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table_idx = table_walk(table_idx, index, &kind);
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}
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if (UNLIKELY(kind != ENTRY_INSTR))
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return kind == 0 ? FD_ERR_UD : FD_ERR_PARTIAL;
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static _Alignas(16) const struct InstrDesc descs[] = {
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#define FD_DECODE_TABLE_DESCS
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#include <fadec-decode-private.inc>
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#undef FD_DECODE_TABLE_DESCS
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};
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const struct InstrDesc* desc = &descs[table_idx >> 2];
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instr->type = desc->type;
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instr->addrsz = addr_size;
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instr->flags = prefix_rep == 2 ? FD_FLAG_REP :
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prefix_rep == 3 ? FD_FLAG_REPNZ : 0;
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if (mode == DECODE_64)
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instr->flags |= FD_FLAG_64;
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instr->address = address;
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for (unsigned i = 0; i < sizeof(instr->operands) / sizeof(FdOp); i++)
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instr->operands[i] = (FdOp) {0};
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if (DESC_MODRM(desc) && UNLIKELY(off++ >= len))
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return FD_ERR_PARTIAL;
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unsigned op_byte = buffer[off - 1] | (!DESC_MODRM(desc) ? 0xc0 : 0);
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unsigned op_size;
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unsigned op_size_alt = 0;
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if (!(DESC_OPSIZE(desc) & 4)) {
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if (DESC_OPSIZE(desc) == 1)
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op_size = 1;
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else if (mode == DECODE_64)
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op_size = ((prefix_rex & PREFIX_REXW) || DESC_OPSIZE(desc) == 3) ? 4 :
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UNLIKELY(prefix_66 && !DESC_IGN66(desc)) ? 2 :
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DESC_OPSIZE(desc) ? 4 :
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3;
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else
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op_size = UNLIKELY(prefix_66 && !DESC_IGN66(desc)) ? 2 : 3;
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} else {
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op_size = 5 + !!(prefix_rex & PREFIX_VEXL);
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op_size_alt = op_size - (DESC_OPSIZE(desc) & 3);
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}
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if (UNLIKELY(instr->type == FDI_MOV_CR || instr->type == FDI_MOV_DR)) {
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unsigned modreg = (op_byte >> 3) & 0x7;
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unsigned modrm = op_byte & 0x7;
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FdOp* op_modreg = &instr->operands[DESC_MODREG_IDX(desc)];
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op_modreg->type = FD_OT_REG;
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op_modreg->reg = modreg | (prefix_rex & PREFIX_REXR ? 8 : 0);
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op_modreg->misc = instr->type == FDI_MOV_CR ? FD_RT_CR : FD_RT_DR;
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if (instr->type == FDI_MOV_CR && (~0x011d >> op_modreg->reg) & 1)
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return FD_ERR_UD;
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else if (instr->type == FDI_MOV_DR && prefix_rex & PREFIX_REXR)
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return FD_ERR_UD;
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FdOp* op_modrm = &instr->operands[DESC_MODRM_IDX(desc)];
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op_modrm->type = FD_OT_REG;
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op_modrm->reg = modrm | (prefix_rex & PREFIX_REXB ? 8 : 0);
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op_modrm->misc = FD_RT_GPL;
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goto skip_modrm;
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}
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if (DESC_HAS_MODREG(desc))
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{
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FdOp* op_modreg = &instr->operands[DESC_MODREG_IDX(desc)];
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unsigned reg_idx = (op_byte & 0x38) >> 3;
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unsigned reg_ty = DESC_REGTY_MODREG(desc); // GPL VEC MSK - MMX SEG
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op_modreg->misc = (0350761 >> (3 * reg_ty)) & 0x7;
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if (LIKELY(!(reg_ty & 4)))
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reg_idx += prefix_rex & PREFIX_REXR ? 8 : 0;
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op_modreg->type = FD_OT_REG;
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op_modreg->reg = reg_idx;
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}
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if (DESC_HAS_MODRM(desc))
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{
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FdOp* op_modrm = &instr->operands[DESC_MODRM_IDX(desc)];
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unsigned mod = op_byte & 0xc0;
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unsigned rm = op_byte & 0x07;
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if (mod == 0xc0)
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{
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uint8_t reg_idx = rm;
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unsigned reg_ty = DESC_REGTY_MODRM(desc); // GPL VEC - - MMX FPU MSK
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op_modrm->misc = (07450061 >> (3 * reg_ty)) & 0x7;
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if (LIKELY(!(reg_ty & 4)))
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reg_idx += prefix_rex & PREFIX_REXB ? 8 : 0;
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op_modrm->type = FD_OT_REG;
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op_modrm->reg = reg_idx;
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}
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else
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{
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bool vsib = UNLIKELY(DESC_VSIB(desc));
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// SIB byte
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uint8_t base = rm;
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if (rm == 4)
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{
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if (UNLIKELY(off >= len))
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return FD_ERR_PARTIAL;
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uint8_t sib = buffer[off++];
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unsigned scale = sib & 0xc0;
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unsigned idx = (sib & 0x38) >> 3;
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idx += prefix_rex & PREFIX_REXX ? 8 : 0;
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base = sib & 0x07;
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if (!vsib && idx == 4)
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idx = FD_REG_NONE;
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op_modrm->misc = scale | idx;
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}
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else
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{
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// VSIB must have a memory operand with SIB byte.
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if (vsib)
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return FD_ERR_UD;
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op_modrm->misc = FD_REG_NONE;
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}
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op_modrm->type = FD_OT_MEM;
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// RIP-relative addressing only if SIB-byte is absent
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if (mod == 0 && rm == 5 && mode == DECODE_64)
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op_modrm->reg = FD_REG_IP;
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else if (mod == 0 && base == 5)
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op_modrm->reg = FD_REG_NONE;
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else
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op_modrm->reg = base + (prefix_rex & PREFIX_REXB ? 8 : 0);
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if (mod == 0x40)
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{
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if (UNLIKELY(off + 1 > len))
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return FD_ERR_PARTIAL;
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instr->disp = (int8_t) LOAD_LE_1(&buffer[off]);
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off += 1;
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}
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else if (mod == 0x80 || (mod == 0 && base == 5))
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{
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if (UNLIKELY(off + 4 > len))
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return FD_ERR_PARTIAL;
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instr->disp = (int32_t) LOAD_LE_4(&buffer[off]);
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off += 4;
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}
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else
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{
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instr->disp = 0;
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}
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}
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}
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skip_modrm:
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if (UNLIKELY(DESC_HAS_VEXREG(desc)))
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{
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// Without VEX prefix, this encodes an implicit register
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FdOp* operand = &instr->operands[DESC_VEXREG_IDX(desc)];
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operand->type = FD_OT_REG;
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if (mode == DECODE_32)
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vex_operand &= 0x7;
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operand->reg = vex_operand | DESC_ZEROREG_VAL(desc);
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unsigned reg_ty = DESC_REGTY_VEXREG(desc); // GPL VEC MSK FPU
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operand->misc = (04761 >> (3 * reg_ty)) & 0x7;
|
|
}
|
|
else if (vex_operand != 0)
|
|
{
|
|
return FD_ERR_UD;
|
|
}
|
|
|
|
uint32_t imm_control = DESC_IMM_CONTROL(desc);
|
|
if (UNLIKELY(imm_control == 1))
|
|
{
|
|
// 1 = immediate constant 1, used for shifts
|
|
FdOp* operand = &instr->operands[DESC_IMM_IDX(desc)];
|
|
operand->type = FD_OT_IMM;
|
|
instr->imm = 1;
|
|
}
|
|
else if (UNLIKELY(imm_control == 2))
|
|
{
|
|
// 2 = memory, address-sized, used for mov with moffs operand
|
|
FdOp* operand = &instr->operands[DESC_IMM_IDX(desc)];
|
|
operand->type = FD_OT_MEM;
|
|
operand->reg = FD_REG_NONE;
|
|
operand->misc = FD_REG_NONE;
|
|
|
|
int moffsz = 1 << addr_size;
|
|
if (UNLIKELY(off + moffsz > len))
|
|
return FD_ERR_PARTIAL;
|
|
if (moffsz == 2)
|
|
instr->disp = LOAD_LE_2(&buffer[off]);
|
|
if (moffsz == 4)
|
|
instr->disp = LOAD_LE_4(&buffer[off]);
|
|
if (LIKELY(moffsz == 8))
|
|
instr->disp = LOAD_LE_8(&buffer[off]);
|
|
off += moffsz;
|
|
}
|
|
else if (UNLIKELY(imm_control == 3))
|
|
{
|
|
// 3 = register in imm8[7:4], used for RVMR encoding with VBLENDVP[SD]
|
|
FdOp* operand = &instr->operands[DESC_IMM_IDX(desc)];
|
|
operand->type = FD_OT_REG;
|
|
operand->misc = FD_RT_VEC;
|
|
|
|
if (UNLIKELY(off + 1 > len))
|
|
return FD_ERR_PARTIAL;
|
|
uint8_t reg = (uint8_t) LOAD_LE_1(&buffer[off]);
|
|
off += 1;
|
|
|
|
if (mode == DECODE_32)
|
|
reg &= 0x7f;
|
|
operand->reg = reg >> 4;
|
|
instr->imm = reg & 0x0f;
|
|
}
|
|
else if (imm_control != 0)
|
|
{
|
|
FdOp* operand = &instr->operands[DESC_IMM_IDX(desc)];
|
|
operand->type = FD_OT_IMM;
|
|
|
|
// 4/5 = immediate, operand-sized/8 bit
|
|
// 6/7 = offset, operand-sized/8 bit (used for jumps/calls)
|
|
int imm_byte = imm_control & 1;
|
|
int imm_offset = imm_control & 2;
|
|
|
|
uint8_t imm_size;
|
|
if (imm_byte)
|
|
imm_size = 1;
|
|
else if (UNLIKELY(instr->type == FDI_RET || instr->type == FDI_RETF ||
|
|
instr->type == FDI_SSE_EXTRQ ||
|
|
instr->type == FDI_SSE_INSERTQ))
|
|
imm_size = 2;
|
|
else if (UNLIKELY(instr->type == FDI_JMPF || instr->type == FDI_CALLF))
|
|
imm_size = (1 << op_size >> 1) + 2;
|
|
else if (UNLIKELY(instr->type == FDI_ENTER))
|
|
imm_size = 3;
|
|
else if (instr->type == FDI_MOVABS)
|
|
imm_size = (1 << op_size >> 1);
|
|
else
|
|
imm_size = op_size == 2 ? 2 : 4;
|
|
|
|
if (UNLIKELY(off + imm_size > len))
|
|
return FD_ERR_PARTIAL;
|
|
|
|
if (imm_size == 1)
|
|
instr->imm = (int8_t) LOAD_LE_1(&buffer[off]);
|
|
else if (imm_size == 2)
|
|
instr->imm = (int16_t) LOAD_LE_2(&buffer[off]);
|
|
else if (imm_size == 3)
|
|
instr->imm = LOAD_LE_3(&buffer[off]);
|
|
else if (imm_size == 4)
|
|
instr->imm = (int32_t) LOAD_LE_4(&buffer[off]);
|
|
else if (imm_size == 6)
|
|
instr->imm = LOAD_LE_4(&buffer[off]) | LOAD_LE_2(&buffer[off+4]) << 32;
|
|
else if (imm_size == 8)
|
|
instr->imm = (int64_t) LOAD_LE_8(&buffer[off]);
|
|
off += imm_size;
|
|
|
|
if (imm_offset)
|
|
{
|
|
if (instr->address != 0)
|
|
instr->imm += instr->address + off;
|
|
else
|
|
operand->type = FD_OT_OFF;
|
|
}
|
|
}
|
|
|
|
if (instr->type == FDI_XCHG_NOP)
|
|
{
|
|
// Only 4890, 90, and 6690 are true NOPs.
|
|
if (instr->operands[0].reg == 0 && instr->operands[1].reg == 0)
|
|
{
|
|
instr->operands[0].type = FD_OT_NONE;
|
|
instr->operands[1].type = FD_OT_NONE;
|
|
instr->type = FDI_NOP;
|
|
}
|
|
else
|
|
{
|
|
instr->type = FDI_XCHG;
|
|
}
|
|
}
|
|
|
|
if (UNLIKELY(instr->type == FDI_3DNOW))
|
|
{
|
|
unsigned opc3dn = instr->imm;
|
|
if (opc3dn & 0x40)
|
|
return FD_ERR_UD;
|
|
uint64_t msk = opc3dn & 0x80 ? 0x88d144d144d14400 : 0x30003000;
|
|
if (!(msk >> (opc3dn & 0x3f) & 1))
|
|
return FD_ERR_UD;
|
|
}
|
|
|
|
if (UNLIKELY(prefix_lock)) {
|
|
if (!DESC_LOCK(desc) || instr->operands[0].type != FD_OT_MEM)
|
|
return FD_ERR_UD;
|
|
instr->flags |= FD_FLAG_LOCK;
|
|
}
|
|
|
|
uint8_t operand_sizes[4] = {
|
|
DESC_SIZE_FIX1(desc), DESC_SIZE_FIX2(desc) + 1, op_size, op_size_alt
|
|
};
|
|
|
|
for (int i = 0; i < 4; i++)
|
|
{
|
|
FdOp* operand = &instr->operands[i];
|
|
if (operand->type == FD_OT_NONE)
|
|
break;
|
|
|
|
operand->size = operand_sizes[(desc->operand_sizes >> 2 * i) & 3];
|
|
}
|
|
|
|
if (UNLIKELY(op_size == 1 || instr->type == FDI_MOVSX || instr->type == FDI_MOVZX)) {
|
|
if (!(prefix_rex & PREFIX_REX)) {
|
|
for (int i = 0; i < 2; i++) {
|
|
FdOp* operand = &instr->operands[i];
|
|
if (operand->type == FD_OT_NONE)
|
|
break;
|
|
if (operand->type == FD_OT_REG && operand->misc == FD_RT_GPL &&
|
|
operand->size == 1 && operand->reg >= 4)
|
|
operand->misc = FD_RT_GPH;
|
|
}
|
|
}
|
|
}
|
|
|
|
instr->size = off;
|
|
instr->operandsz = DESC_INSTR_WIDTH(desc) ? op_size - 1 : 0;
|
|
|
|
return off;
|
|
}
|