395 lines
13 KiB
C
395 lines
13 KiB
C
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#include <stdbool.h>
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#include <stddef.h>
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#include <stdint.h>
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#include <fadec-enc.h>
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#define LIKELY(x) __builtin_expect((x), 1)
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#define UNLIKELY(x) __builtin_expect((x), 0)
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enum {
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// 16:17 = escape
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OPC_0F = 1 << 16,
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OPC_0F38 = 2 << 16,
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OPC_0F3A = 3 << 16,
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OPC_ESCAPE_MSK = 3 << 16,
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OPC_VSIB = 1 << 18,
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OPC_66 = 1 << 19,
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OPC_F2 = 1 << 20,
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OPC_F3 = 1 << 21,
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OPC_REXW = 1 << 22,
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OPC_LOCK = 1 << 23,
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OPC_VEX = 1 << 24,
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OPC_VEXL = 1 << 25,
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OPC_REXR = 1 << 28,
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OPC_REXX = 1 << 27,
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OPC_REXB = 1 << 26,
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OPC_REX = 1 << 29,
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OPC_67 = 1 << 30,
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};
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#define OPC_SEG_IDX 31
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#define OPC_SEG_MSK (0x7l << OPC_SEG_IDX)
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#define OPC_VEXOP_IDX 34
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#define OPC_VEXOP_MSK (0xfl << OPC_VEXOP_IDX)
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static bool op_mem(FeOp op) { return op < 0; }
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static bool op_reg(FeOp op) { return op >= 0; }
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static bool op_reg_gpl(FeOp op) { return (op & ~0xf) == 0x100; }
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static bool op_reg_gph(FeOp op) { return (op & ~0x3) == 0x204; }
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static bool op_reg_seg(FeOp op) { return (op & ~0x7) == 0x300 && (op & 7) < 6; }
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static bool op_reg_fpu(FeOp op) { return (op & ~0x7) == 0x400; }
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static bool op_reg_mmx(FeOp op) { return (op & ~0x7) == 0x500; }
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static bool op_reg_xmm(FeOp op) { return (op & ~0xf) == 0x600; }
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static int64_t op_mem_offset(FeOp op) { return (int32_t) op; }
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static unsigned op_mem_base(FeOp op) { return (op >> 32) & 0xfff; }
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static unsigned op_mem_idx(FeOp op) { return (op >> 44) & 0xfff; }
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static unsigned op_mem_scale(FeOp op) { return (op >> 56) & 0xf; }
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static unsigned op_reg_idx(FeOp op) { return op & 0xff; }
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static bool op_imm_n(FeOp imm, unsigned immsz) {
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if (immsz == 1 && (int8_t) imm != imm) return false;
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if (immsz == 2 && (int16_t) imm != imm) return false;
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if (immsz == 4 && (int32_t) imm != imm) return false;
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return true;
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}
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static
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unsigned
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opc_size(uint64_t opc)
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{
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unsigned res = 1;
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if (opc & OPC_VEX) {
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if ((opc & (OPC_REXW|OPC_REXX|OPC_REXB|OPC_ESCAPE_MSK)) != OPC_0F)
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res += 3;
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else
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res += 2;
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} else {
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if (opc & OPC_66) res++;
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if (opc & OPC_F2) res++;
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if (opc & OPC_F3) res++;
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if (opc & (OPC_REX|OPC_REXW|OPC_REXR|OPC_REXX|OPC_REXB)) res++;
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if (opc & OPC_ESCAPE_MSK) res++;
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if ((opc & OPC_ESCAPE_MSK) == OPC_0F38 || (opc & OPC_ESCAPE_MSK) == OPC_0F3A) res++;
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}
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if (opc & OPC_SEG_MSK) res++;
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if (opc & OPC_67) res++;
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if ((opc & 0xc000) == 0xc000) res++;
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return res;
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}
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static
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int
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enc_opc(uint8_t** restrict buf, uint64_t opc)
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{
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if (opc & OPC_SEG_MSK)
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*(*buf)++ = (0x65643e362e2600 >> (8 * ((opc >> OPC_SEG_IDX) & 7))) & 0xff;
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if (opc & OPC_67) *(*buf)++ = 0x67;
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if (opc & OPC_VEX) {
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bool vex3 = (opc & (OPC_REXW|OPC_REXX|OPC_REXB|OPC_ESCAPE_MSK)) != OPC_0F;
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unsigned pp = 0;
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if (opc & OPC_66) pp = 1;
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if (opc & OPC_F3) pp = 2;
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if (opc & OPC_F2) pp = 3;
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*(*buf)++ = 0xc4 | !vex3;
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unsigned b2 = pp | (opc & OPC_VEXL ? 0x4 : 0);
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if (vex3) {
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unsigned b1 = (opc & OPC_ESCAPE_MSK) >> 16;
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if (!(opc & OPC_REXR)) b1 |= 0x80;
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if (!(opc & OPC_REXX)) b1 |= 0x40;
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if (!(opc & OPC_REXB)) b1 |= 0x20;
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*(*buf)++ = b1;
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if (opc & OPC_REXW) b2 |= 0x80;
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} else {
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if (!(opc & OPC_REXR)) b2 |= 0x80;
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}
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b2 |= (~((opc & OPC_VEXOP_MSK) >> OPC_VEXOP_IDX) & 0xf) << 3;
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*(*buf)++ = b2;
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} else {
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if (opc & OPC_66) *(*buf)++ = 0x66;
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if (opc & OPC_F2) *(*buf)++ = 0xF2;
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if (opc & OPC_F3) *(*buf)++ = 0xF3;
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if (opc & (OPC_REX|OPC_REXW|OPC_REXR|OPC_REXX|OPC_REXB))
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{
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unsigned rex = 0x40;
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if (opc & OPC_REXW) rex |= 8;
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if (opc & OPC_REXR) rex |= 4;
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if (opc & OPC_REXX) rex |= 2;
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if (opc & OPC_REXB) rex |= 1;
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*(*buf)++ = rex;
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}
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if (opc & OPC_ESCAPE_MSK) *(*buf)++ = 0x0F;
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if ((opc & OPC_ESCAPE_MSK) == OPC_0F38) *(*buf)++ = 0x38;
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if ((opc & OPC_ESCAPE_MSK) == OPC_0F3A) *(*buf)++ = 0x3A;
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}
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*(*buf)++ = opc & 0xff;
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if ((opc & 0xc000) == 0xc000) *(*buf)++ = (opc >> 8) & 0xff;
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return 0;
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}
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static
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int
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enc_imm(uint8_t** restrict buf, uint64_t imm, unsigned immsz)
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{
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if (!op_imm_n(imm, immsz)) return -1;
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for (unsigned i = 0; i < immsz; i++)
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*(*buf)++ = imm >> 8 * i;
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return 0;
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}
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static
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int
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enc_o(uint8_t** restrict buf, uint64_t opc, uint64_t op0)
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{
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if (op_reg_idx(op0) & 0x8) opc |= OPC_REXB;
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bool has_rex = !!(opc & (OPC_REX|OPC_REXW|OPC_REXR|OPC_REXX|OPC_REXB));
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if (has_rex && op_reg_gph(op0)) return -1;
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if (enc_opc(buf, opc)) return -1;
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*(*buf - 1) = (*(*buf - 1) & 0xf8) | (op_reg_idx(op0) & 0x7);
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return 0;
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}
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static
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int
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enc_mr(uint8_t** restrict buf, uint64_t opc, uint64_t op0, uint64_t op1,
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unsigned immsz)
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{
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// If !op_reg(op1), it is a constant value for ModRM.reg
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if (op_reg(op0) && (op_reg_idx(op0) & 0x8)) opc |= OPC_REXB;
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if (op_mem(op0) && (op_mem_base(op0) & 0x8)) opc |= OPC_REXB;
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if (op_mem(op0) && (op_mem_idx(op0) & 0x8)) opc |= OPC_REXX;
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if (op_reg(op1) && op_reg_idx(op1) & 0x8) opc |= OPC_REXR;
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bool has_rex = !!(opc & (OPC_REX|OPC_REXW|OPC_REXR|OPC_REXX|OPC_REXB));
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if (has_rex && (op_reg_gph(op0) || op_reg_gph(op1))) return -1;
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int mod = 0, reg = op1 & 7, rm;
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int scale = 0, idx = 4, base = 0;
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int32_t off = 0;
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bool withsib = false, mod0off = false;
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if (op_reg(op0))
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{
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mod = 3;
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rm = op_reg_idx(op0) & 7;
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}
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else
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{
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off = op_mem_offset(op0);
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if (!!op_mem_idx(op0) != !!op_mem_scale(op0)) return -1;
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if (!op_mem_idx(op0) && (opc & OPC_VSIB)) return -1;
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if (op_mem_idx(op0))
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{
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if (opc & OPC_VSIB)
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{
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if (!op_reg_xmm(op_mem_idx(op0))) return -1;
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}
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else
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{
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if (!op_reg_gpl(op_mem_idx(op0))) return -1;
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if (op_reg_idx(op_mem_idx(op0)) == 4) return -1;
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}
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idx = op_mem_idx(op0) & 7;
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int scalabs = op_mem_scale(op0);
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if (scalabs & (scalabs - 1)) return -1;
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scale = (scalabs & 0xA ? 1 : 0) | (scalabs & 0xC ? 2 : 0);
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withsib = true;
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}
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if (!op_mem_base(op0))
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{
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rm = 5;
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mod0off = true;
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withsib = true;
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}
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else if (op_mem_base(op0) == FE_IP)
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{
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rm = 5;
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mod0off = true;
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// Adjust offset, caller doesn't know instruction length.
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off -= opc_size(opc) + 5 + immsz;
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if (withsib) return -1;
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}
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else
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{
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if (!op_reg_gpl(op_mem_base(op0))) return -1;
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rm = op_reg_idx(op_mem_base(op0)) & 7;
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if (rm == 5) mod = 1;
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}
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if (off && op_imm_n(off, 1) && !mod0off)
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mod = 1;
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else if (off && !mod0off)
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mod = 2;
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if (withsib || rm == 4)
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{
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base = rm;
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rm = 4;
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}
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}
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if (enc_opc(buf, opc)) return -1;
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*(*buf)++ = (mod << 6) | (reg << 3) | rm;
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if (mod != 3 && rm == 4)
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*(*buf)++ = (scale << 6) | (idx << 3) | base;
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if (mod == 1) return enc_imm(buf, off, 1);
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if (mod == 2 || mod0off) return enc_imm(buf, off, 4);
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return 0;
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}
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typedef enum {
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ENC_INVALID = 0,
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ENC_NP,
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ENC_M, ENC_M1, ENC_MI, ENC_MC, ENC_MR, ENC_RM, ENC_RMA, ENC_MRI, ENC_RMI, ENC_MRC,
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ENC_AM, ENC_MA,
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ENC_I, ENC_IA, ENC_O, ENC_OI, ENC_OA, ENC_S, ENC_A, ENC_D, ENC_FD, ENC_TD,
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ENC_RVM, ENC_RVMI, ENC_RVMR, ENC_RMV, ENC_VM, ENC_VMI, ENC_MVR,
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ENC_MAX
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} Encoding;
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struct EncodingInfo {
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uint8_t modrm : 2;
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uint8_t modreg : 2;
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uint8_t vexreg : 2;
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uint8_t immidx : 2;
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uint8_t immctl : 3;
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uint8_t zregidx : 2;
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uint8_t zregval : 1;
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};
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const struct EncodingInfo encoding_infos[ENC_MAX] = {
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[ENC_INVALID] = { 0 },
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[ENC_NP] = { 0 },
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[ENC_M] = { .modrm = 0^3 },
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[ENC_M1] = { .modrm = 0^3, .immctl = 1, .immidx = 1 },
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[ENC_MI] = { .modrm = 0^3, .immctl = 4, .immidx = 1 },
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[ENC_MC] = { .modrm = 0^3, .zregidx = 1^3, .zregval = 1 },
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[ENC_MR] = { .modrm = 0^3, .modreg = 1^3 },
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[ENC_RM] = { .modrm = 1^3, .modreg = 0^3 },
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[ENC_RMA] = { .modrm = 1^3, .modreg = 0^3, .zregidx = 2^3, .zregval = 0 },
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[ENC_MRI] = { .modrm = 0^3, .modreg = 1^3, .immctl = 4, .immidx = 2 },
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[ENC_RMI] = { .modrm = 1^3, .modreg = 0^3, .immctl = 4, .immidx = 2 },
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[ENC_MRC] = { .modrm = 0^3, .modreg = 1^3, .zregidx = 2^3, .zregval = 1 },
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[ENC_AM] = { .modrm = 1^3, .zregidx = 0^3, .zregval = 0 },
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[ENC_MA] = { .modrm = 0^3, .zregidx = 1^3, .zregval = 0 },
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[ENC_I] = { .immctl = 4, .immidx = 0 },
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[ENC_IA] = { .zregidx = 0^3, .zregval = 0, .immctl = 4, .immidx = 1 },
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[ENC_O] = { .modreg = 0^3 },
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[ENC_OI] = { .modreg = 0^3, .immctl = 4, .immidx = 1 },
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[ENC_OA] = { .modreg = 0^3, .zregidx = 1^3, .zregval = 0 },
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[ENC_S] = { 0 },
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[ENC_A] = { .zregidx = 0^3, .zregval = 0 },
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[ENC_D] = { .immctl = 6, .immidx = 0 },
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[ENC_FD] = { .immctl = 2, .immidx = 1 },
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[ENC_TD] = { .immctl = 2, .immidx = 0 },
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[ENC_RVM] = { .modrm = 2^3, .modreg = 0^3, .vexreg = 1^3 },
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[ENC_RVMI] = { .modrm = 2^3, .modreg = 0^3, .vexreg = 1^3, .immctl = 4, .immidx = 3 },
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[ENC_RVMR] = { .modrm = 2^3, .modreg = 0^3, .vexreg = 1^3, .immctl = 3, .immidx = 3 },
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[ENC_RMV] = { .modrm = 1^3, .modreg = 0^3, .vexreg = 2^3 },
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[ENC_VM] = { .modrm = 1^3, .vexreg = 0^3 },
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[ENC_VMI] = { .modrm = 1^3, .vexreg = 0^3, .immctl = 4, .immidx = 2 },
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[ENC_MVR] = { .modrm = 0^3, .modreg = 1^3, .vexreg = 1^3 },
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};
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struct EncodeDesc {
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uint64_t opc : 26;
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uint64_t enc : 5;
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uint64_t immsz : 4;
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uint64_t alt : 13;
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uint64_t tys : 16;
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};
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static const struct EncodeDesc descs[] = {
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#include <fadec-enc-cases.inc>
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};
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int
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fe_enc64_impl(uint8_t** restrict buf, uint64_t mnem, FeOp op0, FeOp op1,
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FeOp op2, FeOp op3)
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{
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uint8_t* buf_start = *buf;
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uint64_t ops[4] = {op0, op1, op2, op3};
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uint64_t desc_idx = mnem & FE_MNEM_MASK;
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if (UNLIKELY(desc_idx >= FE_MNEM_MAX)) goto fail;
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do
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{
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const struct EncodeDesc* desc = &descs[desc_idx];
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const struct EncodingInfo* ei = &encoding_infos[desc->enc];
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uint64_t opc = desc->opc;
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int64_t imm = 0xcc;
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if (UNLIKELY(desc->enc == ENC_INVALID)) goto fail;
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if (ei->zregidx)
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if (op_reg_idx(ops[ei->zregidx^3]) != ei->zregval) goto next;
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for (int i = 0; i < 4; i++) {
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unsigned ty = (desc->tys >> (4 * i)) & 0xf;
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FeOp op = ops[i];
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if (ty == 0x0) continue;
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if (ty == 0xf && !op_mem(op)) goto next;
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if (ty == 0x1 && !op_reg_gpl(op)) goto next;
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if (ty == 0x2 && !op_reg_gpl(op) && !op_reg_gph(op)) goto next;
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if (ty == 0x2 && op_reg_gpl(op) && op >= FE_SP) opc |= OPC_REX;
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if (ty == 0x3 && !op_reg_seg(op)) goto next;
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if (ty == 0x4 && !op_reg_fpu(op)) goto next;
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if (ty == 0x5 && !op_reg_mmx(op)) goto next;
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if (ty == 0x6 && !op_reg_xmm(op)) goto next;
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if (UNLIKELY(ty >= 7 && ty < 0xf)) goto next; // TODO: support BND, CR, DR
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}
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if (UNLIKELY(mnem & FE_ADDR32))
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opc |= OPC_67;
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if (UNLIKELY(mnem & FE_SEG_MASK))
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opc |= (mnem & FE_SEG_MASK) << (OPC_SEG_IDX - 16);
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if (ei->immctl > 0) {
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imm = ops[ei->immidx];
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if (ei->immctl == 3)
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imm = op_reg_idx(imm) << 4;
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if (ei->immctl == 6) {
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if (UNLIKELY(mnem & FE_JMPL) && desc->alt) goto next;
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imm -= (int64_t) *buf + opc_size(opc) + desc->immsz;
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}
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if (UNLIKELY(ei->immctl == 1) && imm != 1) goto next;
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if (ei->immctl >= 4 && !op_imm_n(imm, desc->immsz)) goto next;
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}
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// NOP has no operands, so this must be the 32-bit OA XCHG
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if ((desc->opc & ~7) == 0x90 && ops[0] == FE_AX) goto next;
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if (ei->vexreg)
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opc |= ((uint64_t) op_reg_idx(ops[ei->vexreg^3])) << OPC_VEXOP_IDX;
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if (ei->modrm) {
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FeOp modreg = ei->modreg ? ops[ei->modreg^3] : (opc & 0xff00) >> 8;
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if (enc_mr(buf, opc, ops[ei->modrm^3], modreg, desc->immsz)) goto fail;
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} else if (ei->modreg) {
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if (enc_o(buf, opc, ops[ei->modreg^3])) goto fail;
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} else if (UNLIKELY(desc->enc == ENC_S)) {
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if (enc_opc(buf, opc | (op_reg_idx(op0) << 3))) goto fail;
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} else {
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if (enc_opc(buf, opc)) goto fail;
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}
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if (ei->immctl >= 2)
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if (enc_imm(buf, imm, desc->immsz)) goto fail;
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return 0;
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next:
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desc_idx = desc->alt;
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} while (desc_idx != 0);
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fail:
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// Don't advance buffer on error; though we shouldn't write anything.
|
|
*buf = buf_start;
|
|
return -1;
|
|
}
|