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f9bba6289e0839471ff79b1107b8eeb5525ce6be
Commit Graph

55 Commits

Author SHA1 Message Date
Alexis Engelke
f9bba6289e instrs: Annotate only-mem and only-reg in opcode 2020-11-22 11:34:55 +01:00
Alexis Engelke
62b0420147 parseinstr: Simplify opcode naming scheme 2020-11-09 09:47:36 +01:00
Alexis Engelke
9df6ac1788 decode: Replace T8+T72 with T16+T8E for R/M value 2020-11-09 09:47:36 +01:00
Alexis Engelke
7d7e72746e parseinstr: Split escape and opcode 2020-11-09 09:47:36 +01:00
Alexis Engelke
01e1587c5c decode: Move prefix before other opcode extensions 2020-11-09 09:47:36 +01:00
Alexis Engelke
2e7e396325 decode: Remove TABLE_PREFIX_REP and use NFx prefix 2020-11-09 09:47:36 +01:00
Alexis Engelke
69ce124354 encode: Add library for x86-64 encoding 2020-11-09 09:46:38 +01:00
Alexis Engelke
468eeaa249 parseinstrs: Create a separate class for parsed opcode 2020-07-05 14:57:22 +02:00
Alexis Engelke
9b6caeb2ae parseinstrs: Write mnemonics to separate file 2020-07-04 14:35:51 +02:00
Alexis Engelke
dc668691d8 instrs: Specify segment register size 2020-07-04 14:25:22 +02:00
Alexis Engelke
141680e77c instrs: Remove MUSTMEM, encode in operands 2020-07-04 14:24:56 +02:00
Alexis Engelke
da4ad137d8 instrs: Remove redundant IMM_8 2020-07-04 08:55:51 +02:00
Alexis Engelke
7ee9320840 decode: Add second fixed operand size 2020-06-30 22:07:18 +02:00
Alexis Engelke
08490d4503 parseinstrs: Simplify opkind lookup 2020-06-30 21:02:31 +02:00
Alexis Engelke
3221a319d3 instrs: Don't use O-encoding hack for FSTSW 2020-06-27 17:33:58 +02:00
Alexis Engelke
1b5461036e decode: Don't walk escape opcodes in tables 2020-06-27 17:33:58 +02:00
Alexis Engelke
3ad518e22e decode: Store op types early and compact encoding 
* The encoding of operand types in the decode table now only requires 9
  bits instead of the previous 16 bits.
* Operand types are decoded before the operands itself are stored. This
  allows to ignore REX.RB prefixed for specific register types.
 2020-06-27 17:33:58 +02:00
Alexis Engelke
618d90ed42 instrs: Encode memory size for FPU instructions 2020-06-27 17:33:58 +02:00
Alexis Engelke
807d8a817b decode: Change imm_control to get rid of imm_byte 2020-06-19 14:04:17 +02:00
Alexis Engelke
f978785df3 parseinstrs: Make TrieEntry always hashable 2020-06-17 18:36:18 +02:00
Alexis Engelke
93a61a0ff1 parseinstrs: Remove mnemonic from instr bitstruct 2020-06-17 17:16:53 +02:00
Alexis Engelke
38f52c98b5 parseinstrs: Store mnemonic enum entry in trie 2020-06-17 17:08:23 +02:00
Alexis Engelke
af5b36a58e parseinstrs: Don't needlessly convert to bytes 2020-06-17 16:49:27 +02:00
Alexis Engelke
f4b41a7e80 decode: Use uint16_t for trie 2020-06-17 16:44:22 +02:00
Alexis Engelke
1fedc069b6 parseinstrs: Propagate unpacked data for trie 2020-06-17 16:34:27 +02:00
Alexis Engelke
da4cbc237f parseinstr: Use typing.NamedTuple 2020-05-10 14:20:34 +02:00
Alexis Engelke
513a913feb decode: Store CL as register operand for shifts 2020-02-19 16:53:59 +01:00
Alexis Engelke
e65086c76c parseinstr: Separate fields for operand properties 2020-02-16 18:12:07 +01:00
Alexis Engelke
e59117538f parseinstr: Include mnemnonic in flag bitstruct 2020-02-16 18:05:32 +01:00
Alexis Engelke
f6a66ea4fb Use special root table for VEX 
Some instruction opcodes have an entirely different encoding when a VEX
prefix is present. For example, 0f41 is CMOVNO without mandatory
prefixes while VEX.NP.W0.L1.0f41 is KANDW with a mandatory prefix. To
avoid collisions, the VEX prefix is better handled as a completely
separate decode tree, at the cost of a slight increase in table size.
 2020-02-10 20:34:37 +01:00
Alexis Engelke
b376d0d0f8 parser: Use exceptions instead of assertions 2020-02-10 20:34:37 +01:00
Alexis Engelke
19b76c809e Add MMX and several other instructions 2019-11-03 11:56:24 +01:00
Alexis Engelke
bd6c7ceebe Begin enforcing memory operand requirements 2019-11-02 19:21:29 +01:00
Alexis Engelke
32d65fbf19 Fix CR/DR move operand sizes 2019-11-02 19:20:47 +01:00
Alexis Engelke
194a7d6831 Add REP-prefix table 2019-11-02 19:01:23 +01:00
Alexis Engelke
7682541a00 Refactor opcode parsing 2019-11-02 19:00:46 +01:00
Alexis Engelke
8c51339c49 Add moves from/to control/debug registers 2019-11-02 17:09:41 +01:00
Alexis Engelke
3f278bc6cc Store register type in decoded instruction 2019-05-05 12:53:10 +02:00
Alexis Engelke
899278600b Refactor encoding of bit field 2019-05-05 12:26:20 +02:00
Alexis Engelke
dff78c5a86 Support VSIB encoding 2019-04-27 11:16:09 +02:00
Alexis Engelke
14c5590413 Set size of rare memory operands to zero 2019-02-24 17:11:32 +01:00
Alexis Engelke
f7f0b322c7 Enforce mandatory L0/L1 in VEX prefix 2019-02-24 15:45:00 +01:00
Alexis Engelke
b2b29239b1 Disallow LOCK prefix for non-lockable instructions 2019-02-24 09:26:23 +01:00
Alexis Engelke
67ae0f8de8 Store 32-bit and 64-bit data in a single table 2019-02-23 16:33:01 +01:00
Alexis Engelke
256806e4b6 Use argparse 2019-02-23 15:26:04 +01:00
Alexis Engelke
da683d850a Simplify storing of opcode to description mapping 2019-02-23 12:18:50 +01:00
Alexis Engelke
10e7a41972 Simplify handling of 32-bit and 64-bit encodings 2019-02-23 12:06:04 +01:00
Alexis Engelke
50ba38627b Store instruction description as namedtuple 2019-02-23 11:53:25 +01:00
Alexis Engelke
3fbd0ff5b5 Deduplicate tables in addition to instructions 2019-02-23 11:09:24 +01:00
Alexis Engelke
ffa28357ce Support tables with multiple roots 2019-02-23 11:04:57 +01:00