Alexis Engelke
dc668691d8
instrs: Specify segment register size
2020-07-04 14:25:22 +02:00
Alexis Engelke
0da46cba98
instrs: Add missing VEXLIG for compares
2020-07-04 14:25:20 +02:00
Alexis Engelke
c9333ac2c9
instrs: Enforce memory for VSIB encodings
2020-07-04 14:24:59 +02:00
Alexis Engelke
141680e77c
instrs: Remove MUSTMEM, encode in operands
2020-07-04 14:24:56 +02:00
Alexis Engelke
da4ad137d8
instrs: Remove redundant IMM_8
2020-07-04 08:55:51 +02:00
Alexis Engelke
854082a156
instrs: Remove invalid SIZE_8 markers
2020-07-02 08:39:51 +02:00
Alexis Engelke
7333453a19
instrs: Update several operand types and sizes
2020-06-27 19:01:26 +02:00
Alexis Engelke
3221a319d3
instrs: Don't use O-encoding hack for FSTSW
2020-06-27 17:33:58 +02:00
Alexis Engelke
618d90ed42
instrs: Encode memory size for FPU instructions
2020-06-27 17:33:58 +02:00
Alexis Engelke
bb4b195dbe
instrs/sse,avx: Fix several operand sizes
2020-06-25 21:04:10 +02:00
Alexis Engelke
ab5e0c67c1
decode: Don't fall back to memory encoding with 72-table
2020-06-19 14:04:17 +02:00
Alexis Engelke
80ec7ed960
instrs: Fix decoding of XCHG r8, rax
...
Opcode 90 is only a NOP if there is no REX.B.
2020-06-14 13:36:11 +02:00
Alexis Engelke
dc286b14f2
Unify instruction mnemonics [API break]
...
It is a longer standing issue that some instructions like ADD, IMUL, and
SHL have multiple mnemonics for different encoding forms. This is a
relict from a time where such information was not stored in the
instruction decoding. This, however, is no longer the case and therefore
the extra mnemonics just increase the number of cases to be handled by
users.
2020-02-20 10:56:17 +01:00
Alexis Engelke
513a913feb
decode: Store CL as register operand for shifts
2020-02-19 16:53:59 +01:00
Alexis Engelke
f538554bb9
Support various smaller instruction set extensions
...
In particular: VAESNI, ADX, CLDEMOTE, ENQCMD, PCONFIG, WBNOINVD
2020-02-10 20:37:07 +01:00
Alexis Engelke
bf5d0ef292
Improve decoding correctness in very rare cases
2020-02-10 20:36:02 +01:00
Alexis Engelke
e63fa88da4
Minor fixes (RETF, POPCNT, +PDEP, +PEXT)
2020-02-10 17:17:39 +01:00
Alexis Engelke
19b76c809e
Add MMX and several other instructions
2019-11-03 11:56:24 +01:00
Alexis Engelke
c5281e2f58
Add support for several small ISA extensions
2019-11-02 22:17:43 +01:00
Alexis Engelke
7e89bee1f0
Further memory operand annotations
2019-11-02 22:17:20 +01:00
Alexis Engelke
df4e2725d4
Annotate several more memory-only instructions
2019-11-02 21:50:02 +01:00
Alexis Engelke
92e104d411
Finally fix moves from/to CR/DR registers
2019-11-02 21:48:36 +01:00
Alexis Engelke
bd6c7ceebe
Begin enforcing memory operand requirements
2019-11-02 19:21:29 +01:00
Alexis Engelke
32d65fbf19
Fix CR/DR move operand sizes
2019-11-02 19:20:47 +01:00
Alexis Engelke
194a7d6831
Add REP-prefix table
2019-11-02 19:01:23 +01:00
Alexis Engelke
21cea7ff23
Fix GETSEC prefix encoding
2019-11-02 19:00:11 +01:00
Alexis Engelke
5ba2859c7b
Fix ADDSUBPS encoding
2019-11-02 17:53:21 +01:00
Alexis Engelke
194b99065e
Add RSM instruction
2019-11-02 17:32:51 +01:00
Alexis Engelke
d728f8f4af
Fix UD0 encoding
2019-11-02 17:10:22 +01:00
Alexis Engelke
8efc33ca4d
Add LSS/LFS/LGS instructions
2019-11-02 17:10:04 +01:00
Alexis Engelke
8c51339c49
Add moves from/to control/debug registers
2019-11-02 17:09:41 +01:00
Alexis Engelke
9d6e357d54
Add INT1
2019-11-02 17:09:22 +01:00
Alexis Engelke
915c2296c1
Add support for far returns
2019-11-02 17:08:37 +01:00
Alexis Engelke
07709fcdd8
Fix operand ordering of MOV[LH]P[S]
2019-05-06 08:10:50 +02:00
Alexis Engelke
24b79f71b6
Add missing FPU instructions
2019-05-05 12:53:29 +02:00
Alexis Engelke
dff78c5a86
Support VSIB encoding
2019-04-27 11:16:09 +02:00
Alexis Engelke
1b474a04ac
Add support for missing AVX instructions
2019-04-27 11:10:22 +02:00
Alexis Engelke
14c5590413
Set size of rare memory operands to zero
2019-02-24 17:11:32 +01:00
Alexis Engelke
2dd1c99a81
Fix operand size of some SSE instructions
2019-02-24 15:46:09 +01:00
Alexis Engelke
d5d0009070
Distinguish VZEROALL and VZEROUPPER
2019-02-24 15:45:37 +01:00
Alexis Engelke
dfd70eef39
Fix bug with VMOV[DQ] operand width in 32-bit mode
2019-02-24 10:09:18 +01:00
Alexis Engelke
b2b29239b1
Disallow LOCK prefix for non-lockable instructions
2019-02-24 09:26:23 +01:00
Alexis Engelke
1670a52047
Fix decoding of CVTTS[SD]2SI
2019-02-23 16:33:32 +01:00
Alexis Engelke
81224d1748
Fix some FPU instruction operand sizes
2019-02-10 16:17:33 +01:00
Alexis Engelke
b328067e60
Minor update of instruction definitions
2019-02-10 10:49:22 +01:00
Alexis Engelke
617ebe5c8a
Decode additional CET instructions
...
Mainly motivated to decode binaries compiled by recent GCC versions,
which now include CET instructions like endbr64 all over the place.
2018-12-31 13:25:15 +01:00
Alexis Engelke
a3f77dbf49
Initial commit
2018-04-08 13:45:13 +00:00
