Alexis Engelke
8716bd1991
format: Handle offset operands properly
2020-06-14 14:01:14 +02:00
Alexis Engelke
9454f5f746
travis: Remove Travis CI
2020-06-14 13:45:03 +02:00
aengelke
d18b6bb3cf
ci: Add CI via GitHub Actions
2020-06-14 13:43:26 +02:00
Alexis Engelke
80ec7ed960
instrs: Fix decoding of XCHG r8, rax
...
Opcode 90 is only a NOP if there is no REX.B.
2020-06-14 13:36:11 +02:00
Alexis Engelke
c3df15e19b
api: Store index register in operand struct
...
Combined with some reordering of the struct fields, this reduces the
size of an FdInstr from 56 bytes to 48 bytes.
2020-06-14 13:36:01 +02:00
Alexis Engelke
7a364fcada
api: Drop unused internal FD_FLAG_REX
2020-05-17 11:14:52 +02:00
Alexis Engelke
da4cbc237f
parseinstr: Use typing.NamedTuple
2020-05-10 14:20:34 +02:00
Alexis Engelke
afc574503f
Decode jump targets as offset if address is NULL
...
Addresses relative to the actual address of the instruction are decoded
as new offset operand, where the RIP has to be added to obtain the real
value. For backwards compatibility, the new behavior is only exposed if
the address of the instruction is specified as zero.
2020-03-07 14:30:07 +01:00
Alexis Engelke
dc286b14f2
Unify instruction mnemonics [API break]
...
It is a longer standing issue that some instructions like ADD, IMUL, and
SHL have multiple mnemonics for different encoding forms. This is a
relict from a time where such information was not stored in the
instruction decoding. This, however, is no longer the case and therefore
the extra mnemonics just increase the number of cases to be handled by
users.
2020-02-20 10:56:17 +01:00
Alexis Engelke
513a913feb
decode: Store CL as register operand for shifts
2020-02-19 16:53:59 +01:00
Alexis Engelke
e65086c76c
parseinstr: Separate fields for operand properties
2020-02-16 18:12:07 +01:00
Alexis Engelke
e59117538f
parseinstr: Include mnemnonic in flag bitstruct
2020-02-16 18:05:32 +01:00
Alexis Engelke
f538554bb9
Support various smaller instruction set extensions
...
In particular: VAESNI, ADX, CLDEMOTE, ENQCMD, PCONFIG, WBNOINVD
2020-02-10 20:37:07 +01:00
Alexis Engelke
bf5d0ef292
Improve decoding correctness in very rare cases
2020-02-10 20:36:02 +01:00
Alexis Engelke
8572c15973
Handle RVMR encodings correctly in 32-bit mode
...
The most significant bit in the immediate is ingored in 32-bit mode.
2020-02-10 20:34:37 +01:00
Alexis Engelke
f6a66ea4fb
Use special root table for VEX
...
Some instruction opcodes have an entirely different encoding when a VEX
prefix is present. For example, 0f41 is CMOVNO without mandatory
prefixes while VEX.NP.W0.L1.0f41 is KANDW with a mandatory prefix. To
avoid collisions, the VEX prefix is better handled as a completely
separate decode tree, at the cost of a slight increase in table size.
2020-02-10 20:34:37 +01:00
Alexis Engelke
b376d0d0f8
parser: Use exceptions instead of assertions
2020-02-10 20:34:37 +01:00
Alexis Engelke
e73dbb3eea
Be more restrictive with VSIB encodings
2020-02-10 20:34:37 +01:00
Alexis Engelke
e63fa88da4
Minor fixes (RETF, POPCNT, +PDEP, +PEXT)
2020-02-10 17:17:39 +01:00
Alexis Engelke
889a509a5e
Update documentation for latest changes
2019-11-03 11:56:38 +01:00
Alexis Engelke
19b76c809e
Add MMX and several other instructions
2019-11-03 11:56:24 +01:00
Alexis Engelke
2bf33017bc
Reject invalid move to CS
2019-11-03 11:54:00 +01:00
Alexis Engelke
dbfcf33c33
Add more precise error codes
2019-11-02 22:31:10 +01:00
Alexis Engelke
21c40c48d0
Fix compilation error
2019-11-02 22:18:27 +01:00
Alexis Engelke
c5281e2f58
Add support for several small ISA extensions
2019-11-02 22:17:43 +01:00
Alexis Engelke
7e89bee1f0
Further memory operand annotations
2019-11-02 22:17:20 +01:00
Alexis Engelke
dbf72dd282
Fix VEX+REX handling
2019-11-02 22:16:50 +01:00
Alexis Engelke
a5a15258fd
Fix another bug with REX prefix decoding
2019-11-02 21:54:39 +01:00
Alexis Engelke
df4e2725d4
Annotate several more memory-only instructions
2019-11-02 21:50:02 +01:00
Alexis Engelke
92e104d411
Finally fix moves from/to CR/DR registers
2019-11-02 21:48:36 +01:00
Alexis Engelke
96ba1a1166
Verify more register indices
2019-11-02 21:47:28 +01:00
Alexis Engelke
ab2d60da75
Reject invalid segment registers
2019-11-02 21:11:35 +01:00
Alexis Engelke
e2026b572d
Reject invalid VEX encodings
2019-11-02 21:08:34 +01:00
Alexis Engelke
bd6c7ceebe
Begin enforcing memory operand requirements
2019-11-02 19:21:29 +01:00
Alexis Engelke
32d65fbf19
Fix CR/DR move operand sizes
2019-11-02 19:20:47 +01:00
Alexis Engelke
194a7d6831
Add REP-prefix table
2019-11-02 19:01:23 +01:00
Alexis Engelke
7682541a00
Refactor opcode parsing
2019-11-02 19:00:46 +01:00
Alexis Engelke
21cea7ff23
Fix GETSEC prefix encoding
2019-11-02 19:00:11 +01:00
Alexis Engelke
5ba2859c7b
Fix ADDSUBPS encoding
2019-11-02 17:53:21 +01:00
Alexis Engelke
194b99065e
Add RSM instruction
2019-11-02 17:32:51 +01:00
Alexis Engelke
e43ec050af
Correctly handle mis-placed REX prefix
2019-11-02 17:32:40 +01:00
Alexis Engelke
d728f8f4af
Fix UD0 encoding
2019-11-02 17:10:22 +01:00
Alexis Engelke
8efc33ca4d
Add LSS/LFS/LGS instructions
2019-11-02 17:10:04 +01:00
Alexis Engelke
8c51339c49
Add moves from/to control/debug registers
2019-11-02 17:09:41 +01:00
Alexis Engelke
9d6e357d54
Add INT1
2019-11-02 17:09:22 +01:00
Alexis Engelke
a2a28b7342
Fix immediate size for REX+66 combinations
2019-11-02 17:08:58 +01:00
Alexis Engelke
915c2296c1
Add support for far returns
2019-11-02 17:08:37 +01:00
Alexis Engelke
c4a4df458d
Be more restrictive about VEX prefix combinations
2019-11-02 15:53:00 +01:00
Alexis Engelke
5613adda25
Support decoding SS segment override prefix
2019-11-02 15:52:45 +01:00
Alexis Engelke
9987f47a50
meson: Fix warning about missing warning
2019-08-18 18:16:54 +02:00
