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c5f5fa1f75d09098d4a8b184a8db2a87b555ff00
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120 Commits

Author SHA1 Message Date
Alexis Engelke
fcb39f5cbe instrs: Add support for AESKL/AESKLE 2021-01-10 14:15:14 +01:00
Alexis Engelke
862b6d285c instrs: Minor operand size fixes 2021-01-10 14:13:44 +01:00
Alexis Engelke
d40ee6db66 instrs: Add FLD and fix FUCOMIP instructions 2021-01-10 14:08:29 +01:00
Alexis Engelke
c87264ace3 instrs: Add MMX PSHUFW instruction 2021-01-10 14:02:39 +01:00
Alexis Engelke
dd4263b169 instrs: Support far jumps/calls encoded target 2021-01-10 12:31:07 +01:00
Alexis Engelke
2f295e5476 instrs: Exact register size for scalar VEX ops 2021-01-10 12:15:49 +01:00
Alexis Engelke
96e513c8ea breaking! instrs: Decode VMOVS[SD] loads correctly 
These instruction ignore the VEX operand if the source operand is a
memory location.

API compatibility: separate handling for different operand types in the
second and third operand (REG+REG vs. MEM+NONE) is needed.
 2021-01-10 12:12:26 +01:00
Alexis Engelke
e86ea540b5 instrs: Fixup register decoding for PEXTR* 2021-01-10 12:11:27 +01:00
Alexis Engelke
a81582cc3a breaking! instrs: Decode MOVLHPS/MOVHLPS 
Now that we support different /r and /m encodings on the same opcode, we
can easily identify MOVLHPS/MOVHLPS as different instructions.

API compatibility: existing code can point the new MOVLHPS/MOVHLPS
mnemonics to the existing handler for MOVHPS/MOVLPS.
 2021-01-10 12:11:27 +01:00
Alexis Engelke
111769832f format: Properly output VSIB encodings 2021-01-08 10:37:13 +01:00
Alexis Engelke
d8c7ee94b7 instrs: Minor fixes to operand sizes 2021-01-03 20:08:34 +01:00
Alexis Engelke
d2bf961b77 instrs: Properly handle PUSH/POP of SEG registers 2021-01-03 20:08:34 +01:00
Alexis Engelke
aa1a39bd9d instrs: Check SREG validity using modreg table 2020-11-29 11:56:08 +01:00
Alexis Engelke
7ab5a18cb0 instrs: Fix naming of some FMA instructions 2020-11-28 13:54:51 +01:00
Alexis Engelke
8ab9f641b8 instrs: Add TSXLDTRK, AVX_VNNI, HRESET, and UINTR 2020-11-22 17:36:12 +01:00
Alexis Engelke
ad1f1e39c3 decode: Minor non-functional changes 2020-11-22 15:14:57 +01:00
Alexis Engelke
6fe5500444 instrs: Force RIP access to 64-bit and fix XBEGIN 2020-11-22 15:13:52 +01:00
Alexis Engelke
f9bba6289e instrs: Annotate only-mem and only-reg in opcode 2020-11-22 11:34:55 +01:00
Alexis Engelke
62b0420147 parseinstr: Simplify opcode naming scheme 2020-11-09 09:47:36 +01:00
Alexis Engelke
2e7e396325 decode: Remove TABLE_PREFIX_REP and use NFx prefix 2020-11-09 09:47:36 +01:00
Alexis Engelke
69ce124354 encode: Add library for x86-64 encoding 2020-11-09 09:46:38 +01:00
Alexis Engelke
4e95c8d152 instrs: Several operand size and AVX-related fixes 2020-07-05 14:59:24 +02:00
Alexis Engelke
9d7aeb2b61 instrs: Replace LIG attribute with LIG specifier 2020-07-05 14:57:22 +02:00
Alexis Engelke
dc668691d8 instrs: Specify segment register size 2020-07-04 14:25:22 +02:00
Alexis Engelke
0da46cba98 instrs: Add missing VEXLIG for compares 2020-07-04 14:25:20 +02:00
Alexis Engelke
c9333ac2c9 instrs: Enforce memory for VSIB encodings 2020-07-04 14:24:59 +02:00
Alexis Engelke
141680e77c instrs: Remove MUSTMEM, encode in operands 2020-07-04 14:24:56 +02:00
Alexis Engelke
da4ad137d8 instrs: Remove redundant IMM_8 2020-07-04 08:55:51 +02:00
Alexis Engelke
854082a156 instrs: Remove invalid SIZE_8 markers 2020-07-02 08:39:51 +02:00
Alexis Engelke
7333453a19 instrs: Update several operand types and sizes 2020-06-27 19:01:26 +02:00
Alexis Engelke
3221a319d3 instrs: Don't use O-encoding hack for FSTSW 2020-06-27 17:33:58 +02:00
Alexis Engelke
618d90ed42 instrs: Encode memory size for FPU instructions 2020-06-27 17:33:58 +02:00
Alexis Engelke
bb4b195dbe instrs/sse,avx: Fix several operand sizes 2020-06-25 21:04:10 +02:00
Alexis Engelke
ab5e0c67c1 decode: Don't fall back to memory encoding with 72-table 2020-06-19 14:04:17 +02:00
Alexis Engelke
80ec7ed960 instrs: Fix decoding of XCHG r8, rax 
Opcode 90 is only a NOP if there is no REX.B.
 2020-06-14 13:36:11 +02:00
Alexis Engelke
dc286b14f2 Unify instruction mnemonics [API break] 
It is a longer standing issue that some instructions like ADD, IMUL, and
SHL have multiple mnemonics for different encoding forms. This is a
relict from a time where such information was not stored in the
instruction decoding. This, however, is no longer the case and therefore
the extra mnemonics just increase the number of cases to be handled by
users.
 2020-02-20 10:56:17 +01:00
Alexis Engelke
513a913feb decode: Store CL as register operand for shifts 2020-02-19 16:53:59 +01:00
Alexis Engelke
f538554bb9 Support various smaller instruction set extensions 
In particular: VAESNI, ADX, CLDEMOTE, ENQCMD, PCONFIG, WBNOINVD
 2020-02-10 20:37:07 +01:00
Alexis Engelke
bf5d0ef292 Improve decoding correctness in very rare cases 2020-02-10 20:36:02 +01:00
Alexis Engelke
e63fa88da4 Minor fixes (RETF, POPCNT, +PDEP, +PEXT) 2020-02-10 17:17:39 +01:00
Alexis Engelke
19b76c809e Add MMX and several other instructions 2019-11-03 11:56:24 +01:00
Alexis Engelke
c5281e2f58 Add support for several small ISA extensions 2019-11-02 22:17:43 +01:00
Alexis Engelke
7e89bee1f0 Further memory operand annotations 2019-11-02 22:17:20 +01:00
Alexis Engelke
df4e2725d4 Annotate several more memory-only instructions 2019-11-02 21:50:02 +01:00
Alexis Engelke
92e104d411 Finally fix moves from/to CR/DR registers 2019-11-02 21:48:36 +01:00
Alexis Engelke
bd6c7ceebe Begin enforcing memory operand requirements 2019-11-02 19:21:29 +01:00
Alexis Engelke
32d65fbf19 Fix CR/DR move operand sizes 2019-11-02 19:20:47 +01:00
Alexis Engelke
194a7d6831 Add REP-prefix table 2019-11-02 19:01:23 +01:00
Alexis Engelke
21cea7ff23 Fix GETSEC prefix encoding 2019-11-02 19:00:11 +01:00
Alexis Engelke
5ba2859c7b Fix ADDSUBPS encoding 2019-11-02 17:53:21 +01:00