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106 Commits

Author SHA1 Message Date
Alexis Engelke
80ec7ed960 instrs: Fix decoding of XCHG r8, rax 
Opcode 90 is only a NOP if there is no REX.B.
 2020-06-14 13:36:11 +02:00
Alexis Engelke
c3df15e19b api: Store index register in operand struct 
Combined with some reordering of the struct fields, this reduces the
size of an FdInstr from 56 bytes to 48 bytes.
 2020-06-14 13:36:01 +02:00
Alexis Engelke
7a364fcada api: Drop unused internal FD_FLAG_REX 2020-05-17 11:14:52 +02:00
Alexis Engelke
afc574503f Decode jump targets as offset if address is NULL 
Addresses relative to the actual address of the instruction are decoded
as new offset operand, where the RIP has to be added to obtain the real
value. For backwards compatibility, the new behavior is only exposed if
the address of the instruction is specified as zero.
 2020-03-07 14:30:07 +01:00
Alexis Engelke
dc286b14f2 Unify instruction mnemonics [API break] 
It is a longer standing issue that some instructions like ADD, IMUL, and
SHL have multiple mnemonics for different encoding forms. This is a
relict from a time where such information was not stored in the
instruction decoding. This, however, is no longer the case and therefore
the extra mnemonics just increase the number of cases to be handled by
users.
 2020-02-20 10:56:17 +01:00
Alexis Engelke
513a913feb decode: Store CL as register operand for shifts 2020-02-19 16:53:59 +01:00
Alexis Engelke
8572c15973 Handle RVMR encodings correctly in 32-bit mode 
The most significant bit in the immediate is ingored in 32-bit mode.
 2020-02-10 20:34:37 +01:00
Alexis Engelke
f6a66ea4fb Use special root table for VEX 
Some instruction opcodes have an entirely different encoding when a VEX
prefix is present. For example, 0f41 is CMOVNO without mandatory
prefixes while VEX.NP.W0.L1.0f41 is KANDW with a mandatory prefix. To
avoid collisions, the VEX prefix is better handled as a completely
separate decode tree, at the cost of a slight increase in table size.
 2020-02-10 20:34:37 +01:00
Alexis Engelke
e73dbb3eea Be more restrictive with VSIB encodings 2020-02-10 20:34:37 +01:00
Alexis Engelke
19b76c809e Add MMX and several other instructions 2019-11-03 11:56:24 +01:00
Alexis Engelke
2bf33017bc Reject invalid move to CS 2019-11-03 11:54:00 +01:00
Alexis Engelke
dbfcf33c33 Add more precise error codes 2019-11-02 22:31:10 +01:00
Alexis Engelke
21c40c48d0 Fix compilation error 2019-11-02 22:18:27 +01:00
Alexis Engelke
dbf72dd282 Fix VEX+REX handling 2019-11-02 22:16:50 +01:00
Alexis Engelke
a5a15258fd Fix another bug with REX prefix decoding 2019-11-02 21:54:39 +01:00
Alexis Engelke
92e104d411 Finally fix moves from/to CR/DR registers 2019-11-02 21:48:36 +01:00
Alexis Engelke
96ba1a1166 Verify more register indices 2019-11-02 21:47:28 +01:00
Alexis Engelke
ab2d60da75 Reject invalid segment registers 2019-11-02 21:11:35 +01:00
Alexis Engelke
e2026b572d Reject invalid VEX encodings 2019-11-02 21:08:34 +01:00
Alexis Engelke
bd6c7ceebe Begin enforcing memory operand requirements 2019-11-02 19:21:29 +01:00
Alexis Engelke
194a7d6831 Add REP-prefix table 2019-11-02 19:01:23 +01:00
Alexis Engelke
e43ec050af Correctly handle mis-placed REX prefix 2019-11-02 17:32:40 +01:00
Alexis Engelke
a2a28b7342 Fix immediate size for REX+66 combinations 2019-11-02 17:08:58 +01:00
Alexis Engelke
915c2296c1 Add support for far returns 2019-11-02 17:08:37 +01:00
Alexis Engelke
c4a4df458d Be more restrictive about VEX prefix combinations 2019-11-02 15:53:00 +01:00
Alexis Engelke
5613adda25 Support decoding SS segment override prefix 2019-11-02 15:52:45 +01:00
Alexis Engelke
bb3c7a4a4f Fix alignment warnings from Clang 2019-08-18 18:13:39 +02:00
Alexis Engelke
c59319b3bb Rename decode tables to fadec-decode-table.inc 2019-06-16 09:45:51 +02:00
Alexis Engelke
3f278bc6cc Store register type in decoded instruction 2019-05-05 12:53:10 +02:00
Alexis Engelke
dff78c5a86 Support VSIB encoding 2019-04-27 11:16:09 +02:00
Alexis Engelke
a7d4c7be9d Minor clean-up 2019-04-27 11:09:57 +02:00
Alexis Engelke
db1ec271df Simplify macros for immediate loading 2019-04-27 08:19:33 +02:00
Alexis Engelke
1ff0e60ddc Remove unused macros 2019-04-27 08:19:03 +02:00
Alexis Engelke
53ca6a2f23 Drop export of VEX.L prefix 
This was previously needed to distinguish VZEROALL and VZEROUPPER. As
mandatory VEX.L is now handled properly, there is no need to export this
encoding detail any longer.
 2019-02-24 15:48:08 +01:00
Alexis Engelke
f7f0b322c7 Enforce mandatory L0/L1 in VEX prefix 2019-02-24 15:45:00 +01:00
Alexis Engelke
9cdd35f82f Decode VEX compact escapes more precisely 
The single opcode byte follows the VEX prefix immediately.
 2019-02-24 10:08:41 +01:00
Alexis Engelke
b2b29239b1 Disallow LOCK prefix for non-lockable instructions 2019-02-24 09:26:23 +01:00
Alexis Engelke
89d6b5a5a7 Refactor ModRM decoding 2019-02-24 09:25:19 +01:00
Alexis Engelke
67ae0f8de8 Store 32-bit and 64-bit data in a single table 2019-02-23 16:33:01 +01:00
Alexis Engelke
dd86caa7f9 Fix RIP-relative address decoding 2019-02-03 20:31:49 +01:00
Alexis Engelke
e9878785da Replace FD_OP with FD_OT to avoid macro collision 2019-02-03 20:31:27 +01:00
Alexis Engelke
3abf29d63e Major rework of API and improved documentation 2019-01-23 20:03:40 +01:00
Alexis Engelke
a045588999 Remove some likeliness information 
Much better information and performance can be achieved using PGO.
 2019-01-22 13:47:37 +01:00
Alexis Engelke
20f6e8c073 Fix handling of 66h prefix on jumps 
It turns out that in x86-64 mode, address and operand size overrides are
ignored by the processor. (Tested that on a real machine.)

Even libopcodes gets this wrong...
 2019-01-14 19:53:46 +01:00
Alexis Engelke
a799024066 Specify address via parameter 
This allows to decode instructions where the address of the buffer is
not the address of the instruction.
 2019-01-14 19:52:03 +01:00
Alexis Engelke
2d1a9582b8 Handle prefix ordering correctly 2019-01-13 20:36:02 +01:00
Alexis Engelke
3ed7cb4a96 No longer expose PrefixSet in header 2019-01-13 18:43:46 +01:00
Alexis Engelke
9d3f34bcc6 No longer store sizes as bitfields 
On most (x86) processors, using bitfields is low than using slightly
more memory.
 2019-01-13 16:19:41 +01:00
Alexis Engelke
5bdafbbcf0 Fix VEX decoding with mandatory VEX.W bit 
The Intel documentation is, well, inconsistent about this: at one point,
they say that the VEX.W prefix is ignored entirely in 32-bit mode, but
the instruction description indicates that a VEX.W can be required in
32-bit/compatibility mode as well.
 2019-01-13 15:56:39 +01:00
Alexis Engelke
5532602000 Refactor prefix decoder 2019-01-13 15:54:47 +01:00