diff --git a/instrs.txt b/instrs.txt
index f52ac6a..465c569 100644
--- a/instrs.txt
+++ b/instrs.txt
@@ -139,9 +139,9 @@
 89                    MR    GP     GP     -      -      MOV
 8a                    RM    GP     GP     -      -      MOV SIZE_8
 8b                    RM    GP     GP     -      -      MOV
-8c                    MR    GP     SREG   -      -      MOV_S2G
+8c                    MR    GP16   SREG   -      -      MOV_S2G
 8d                    RM    GP     MEMZ   -      -      LEA
-8e                    RM    SREG   GP     -      -      MOV_G2S
+8e                    RM    SREG   GP16   -      -      MOV_G2S
 8f/0                  M     GP     -      -      -      POP DEF64
 # Against frequent belief, only, XCHG (r/e)AX, (r)AX with 90 is NOP.
 # As a lacking REX.B cannot be specified here, this is hardcoded.
diff --git a/parseinstrs.py b/parseinstrs.py
index fa27ae1..0423196 100644
--- a/parseinstrs.py
+++ b/parseinstrs.py
@@ -110,7 +110,7 @@ OPKINDS = {
     "XMM64": OpKind(8, "XMM"),
     "XMM128": OpKind(16, "XMM"),
     "XMM256": OpKind(32, "XMM"),
-    "SREG": OpKind(0, "SEG"),
+    "SREG": OpKind(2, "SEG"),
     "FPU": OpKind(10, "FPU"),
     "MEM": OpKind(OpKind.SZ_OP, OpKind.K_MEM),
     "MEMV": OpKind(OpKind.SZ_VEC, OpKind.K_MEM),
diff --git a/tests/test_decode.c b/tests/test_decode.c
index a7e02b1..4f271f9 100644
--- a/tests/test_decode.c
+++ b/tests/test_decode.c
@@ -86,9 +86,9 @@ main(int argc, char** argv)
     TEST64("\x0f\x20\xd0", "[MOV_CR reg8:r0 reg0:r2]");
     TEST64("\x44\x0f\x20\x08", "UD");
     TEST64("\x44\x0f\x21\x00", "UD");
-    TEST("\x8c\xc0", "[MOV_S2G reg4:r0 reg0:r0]");
-    TEST64("\x44\x8c\xc0", "[MOV_S2G reg4:r0 reg0:r0]");
-    TEST("\x8e\xc0", "[MOV_G2S reg0:r0 reg4:r0]");
+    TEST("\x8c\xc0", "[MOV_S2G reg2:r0 reg2:r0]");
+    TEST64("\x44\x8c\xc0", "[MOV_S2G reg2:r0 reg2:r0]");
+    TEST("\x8e\xc0", "[MOV_G2S reg2:r0 reg2:r0]");
     TEST("\x8e\xc8", "UD"); // No mov cs, eax
     TEST("\xd8\xc1", "[FADD reg0:r0 reg0:r1]");
     TEST64("\x41\xd8\xc1", "[FADD reg0:r0 reg0:r1]");