From d40ee6db6694660d60dd090f23c55dfcfb0ee512 Mon Sep 17 00:00:00 2001 From: Alexis Engelke Date: Sun, 10 Jan 2021 14:03:43 +0100 Subject: [PATCH] instrs: Add FLD and fix FUCOMIP instructions --- instrs.txt | 3 ++- tests/test_decode.c | 10 ++++++++++ 2 files changed, 12 insertions(+), 1 deletion(-) diff --git a/instrs.txt b/instrs.txt index 495a891..c57083e 100644 --- a/instrs.txt +++ b/instrs.txt @@ -1294,6 +1294,7 @@ d9/4m M MEMZ - - - FLDENV d9/5m M MEM16 - - - FLDCW d9/6m M MEMZ - - - FSTENV d9/7m M MEM16 - - - FSTCW +d9/0r M FPU - - - FLD d9/1r M FPU - - - FXCH d9d0 NP - - - - FNOP d9e0 NP - - - - FCHS @@ -1401,8 +1402,8 @@ df/6m M FPU - - - FBSTP df/7m M MEM64 - - - FISTP ENC_SEPSZ # FSTSW AX dfe0 A GP16 - - - FSTSW +df/5r AM FPU FPU - - FUCOMIP df/6r AM FPU FPU - - FCOMIP -df/7r AM FPU FPU - - FUCOMIP # # Control Flow Enforcement F3.0f01/5m M GP64 - - - RSTORSSP diff --git a/tests/test_decode.c b/tests/test_decode.c index bf818dc..8c2a992 100644 --- a/tests/test_decode.c +++ b/tests/test_decode.c @@ -323,6 +323,16 @@ main(int argc, char** argv) TEST64("\x40\xc5\xf2\x2a\xc0", "UD"); // VEX+REX TEST64("\x40\x26\xc5\xf2\x2a\xc0", "vcvtsi2ss xmm0, xmm1, eax"); // VEX+REX, but REX doesn't precede VEX + TEST32("\xd9\x00", "fld dword ptr [eax]"); + TEST64("\xd9\x00", "fld dword ptr [rax]"); + TEST32("\xdd\x00", "fld qword ptr [eax]"); + TEST64("\xdd\x00", "fld qword ptr [rax]"); + TEST32("\xdb\x28", "fld tbyte ptr [eax]"); + TEST64("\xdb\x28", "fld tbyte ptr [rax]"); + TEST("\xd9\xc1", "fld st(1)"); + TEST("\xdf\xe9", "fucomip st(0), st(1)"); + TEST64("\x45\xdf\xe9", "fucomip st(0), st(1)"); // REX.RB are ignored. + TEST32("\xf3\x0f\x7e\x5c\x24\x08", "movq xmm3, qword ptr [esp+0x8]"); TEST64("\xf3\x0f\x7e\x5c\x24\x08", "movq xmm3, qword ptr [rsp+0x8]"); TEST32("\xc4\xe1\x00\x58\xc1", "vaddps xmm0, xmm7, xmm1"); // MSB in vvvv ignored