Disallow LOCK prefix for non-lockable instructions
This commit is contained in:
Alexis Engelke
14
decode.c
14
decode.c
@@ -297,10 +297,11 @@ struct InstrDesc
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uint8_t operand_sizes;
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uint8_t immediate;
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uint32_t gp_size_8 : 1;
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uint32_t gp_size_def64 : 1;
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uint32_t gp_instr_width : 1;
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uint32_t gp_fixed_operand_size : 3;
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uint8_t gp_size_8 : 1;
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uint8_t gp_size_def64 : 1;
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uint8_t gp_instr_width : 1;
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uint8_t gp_fixed_operand_size : 3;
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uint8_t lock : 1;
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} __attribute__((packed));
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#define DESC_HAS_MODRM(desc) (((desc)->operand_indices & (3 << 0)) != 0)
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@@ -616,6 +617,11 @@ fd_decode(const uint8_t* buffer, size_t len_sz, int mode_int, uintptr_t address,
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}
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}
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if ((prefixes & PREFIX_LOCK) && !desc->lock)
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return -1;
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if ((prefixes & PREFIX_LOCK) && instr->operands[0].type != FD_OT_MEM)
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return -1;
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instr->size = off;
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return off;
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126
instrs.txt
126
instrs.txt
@@ -1,53 +1,53 @@
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00 MR GP GP - - ADD SIZE_8
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01 MR GP GP - - ADD
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00 MR GP GP - - ADD SIZE_8 LOCK
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01 MR GP GP - - ADD LOCK
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02 RM GP GP - - ADD SIZE_8
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03 RM GP GP - - ADD
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04 IA GP IMM - - ADD_IMM SIZE_8 IMM_8
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05 IA GP IMM - - ADD_IMM
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06 NP - - - - PUSH_ES ONLY32
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07 NP - - - - POP_ES ONLY32
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08 MR GP GP - - OR SIZE_8
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09 MR GP GP - - OR
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08 MR GP GP - - OR SIZE_8 LOCK
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09 MR GP GP - - OR LOCK
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0a RM GP GP - - OR SIZE_8
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0b RM GP GP - - OR
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0c IA GP IMM - - OR_IMM SIZE_8 IMM_8
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0d IA GP IMM - - OR_IMM
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0e NP - - - - PUSH_CS ONLY32
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#0f escape opcode
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10 MR GP GP - - ADC SIZE_8
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11 MR GP GP - - ADC
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10 MR GP GP - - ADC SIZE_8 LOCK
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11 MR GP GP - - ADC LOCK
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12 RM GP GP - - ADC SIZE_8
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13 RM GP GP - - ADC
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14 IA GP IMM - - ADC_IMM SIZE_8 IMM_8
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15 IA GP IMM - - ADC_IMM
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16 NP - - - - PUSH_SS ONLY32
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17 NP - - - - POP_SS ONLY32
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18 MR GP GP - - SBB SIZE_8
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19 MR GP GP - - SBB
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18 MR GP GP - - SBB SIZE_8 LOCK
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19 MR GP GP - - SBB LOCK
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1a RM GP GP - - SBB SIZE_8
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1b RM GP GP - - SBB
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1c IA GP IMM - - SBB_IMM SIZE_8 IMM_8
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1d IA GP IMM - - SBB_IMM
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1e NP - - - - PUSH_DS ONLY32
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1f NP - - - - POP_DS ONLY32
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20 MR GP GP - - AND SIZE_8
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21 MR GP GP - - AND
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20 MR GP GP - - AND SIZE_8 LOCK
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21 MR GP GP - - AND LOCK
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22 RM GP GP - - AND SIZE_8
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23 RM GP GP - - AND
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24 IA GP IMM - - AND_IMM SIZE_8 IMM_8
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25 IA GP IMM - - AND_IMM
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#26 SEG=ES prefix
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27 NP - - - - DAA ONLY32
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28 MR GP GP - - SUB SIZE_8
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29 MR GP GP - - SUB
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28 MR GP GP - - SUB SIZE_8 LOCK
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29 MR GP GP - - SUB LOCK
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2a RM GP GP - - SUB SIZE_8
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2b RM GP GP - - SUB
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2c IA GP IMM - - SUB_IMM SIZE_8 IMM_8
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2d IA GP IMM - - SUB_IMM
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#2e SEG=CS prefix
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2f NP - - - - DAS ONLY32
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30 MR GP GP - - XOR SIZE_8
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31 MR GP GP - - XOR
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30 MR GP GP - - XOR SIZE_8 LOCK
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31 MR GP GP - - XOR LOCK
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32 RM GP GP - - XOR SIZE_8
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33 RM GP GP - - XOR
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34 IA GP IMM - - XOR_IMM SIZE_8 IMM_8
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@@ -99,42 +99,42 @@
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7d D IMM - - - JGE DEF64 IMM_8
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7e D IMM - - - JLE DEF64 IMM_8
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7f D IMM - - - JG DEF64 IMM_8
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80/0 MI GP IMM - - ADD_IMM IMM_8 SIZE_8
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80/1 MI GP IMM - - OR_IMM IMM_8 SIZE_8
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80/2 MI GP IMM - - ADC_IMM IMM_8 SIZE_8
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80/3 MI GP IMM - - SBB_IMM IMM_8 SIZE_8
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80/4 MI GP IMM - - AND_IMM IMM_8 SIZE_8
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80/5 MI GP IMM - - SUB_IMM IMM_8 SIZE_8
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80/6 MI GP IMM - - XOR_IMM IMM_8 SIZE_8
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80/0 MI GP IMM - - ADD_IMM IMM_8 SIZE_8 LOCK
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80/1 MI GP IMM - - OR_IMM IMM_8 SIZE_8 LOCK
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80/2 MI GP IMM - - ADC_IMM IMM_8 SIZE_8 LOCK
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80/3 MI GP IMM - - SBB_IMM IMM_8 SIZE_8 LOCK
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80/4 MI GP IMM - - AND_IMM IMM_8 SIZE_8 LOCK
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80/5 MI GP IMM - - SUB_IMM IMM_8 SIZE_8 LOCK
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80/6 MI GP IMM - - XOR_IMM IMM_8 SIZE_8 LOCK
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80/7 MI GP IMM - - CMP_IMM IMM_8 SIZE_8
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81/0 MI GP IMM - - ADD_IMM
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81/1 MI GP IMM - - OR_IMM
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81/2 MI GP IMM - - ADC_IMM
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81/3 MI GP IMM - - SBB_IMM
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81/4 MI GP IMM - - AND_IMM
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81/5 MI GP IMM - - SUB_IMM
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81/6 MI GP IMM - - XOR_IMM
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81/0 MI GP IMM - - ADD_IMM LOCK
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81/1 MI GP IMM - - OR_IMM LOCK
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81/2 MI GP IMM - - ADC_IMM LOCK
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81/3 MI GP IMM - - SBB_IMM LOCK
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81/4 MI GP IMM - - AND_IMM LOCK
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81/5 MI GP IMM - - SUB_IMM LOCK
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81/6 MI GP IMM - - XOR_IMM LOCK
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81/7 MI GP IMM - - CMP_IMM
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82/0 MI GP IMM - - ADD_IMM ONLY32 IMM_8 SIZE_8
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82/1 MI GP IMM - - OR_IMM ONLY32 IMM_8 SIZE_8
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82/2 MI GP IMM - - ADC_IMM ONLY32 IMM_8 SIZE_8
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82/3 MI GP IMM - - SBB_IMM ONLY32 IMM_8 SIZE_8
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82/4 MI GP IMM - - AND_IMM ONLY32 IMM_8 SIZE_8
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82/5 MI GP IMM - - SUB_IMM ONLY32 IMM_8 SIZE_8
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82/6 MI GP IMM - - XOR_IMM ONLY32 IMM_8 SIZE_8
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82/0 MI GP IMM - - ADD_IMM ONLY32 IMM_8 SIZE_8 LOCK
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82/1 MI GP IMM - - OR_IMM ONLY32 IMM_8 SIZE_8 LOCK
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82/2 MI GP IMM - - ADC_IMM ONLY32 IMM_8 SIZE_8 LOCK
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82/3 MI GP IMM - - SBB_IMM ONLY32 IMM_8 SIZE_8 LOCK
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82/4 MI GP IMM - - AND_IMM ONLY32 IMM_8 SIZE_8 LOCK
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82/5 MI GP IMM - - SUB_IMM ONLY32 IMM_8 SIZE_8 LOCK
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82/6 MI GP IMM - - XOR_IMM ONLY32 IMM_8 SIZE_8 LOCK
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82/7 MI GP IMM - - CMP_IMM ONLY32 IMM_8 SIZE_8
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83/0 MI GP IMM - - ADD_IMM IMM_8
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83/1 MI GP IMM - - OR_IMM IMM_8
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83/2 MI GP IMM - - ADC_IMM IMM_8
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83/3 MI GP IMM - - SBB_IMM IMM_8
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83/4 MI GP IMM - - AND_IMM IMM_8
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83/5 MI GP IMM - - SUB_IMM IMM_8
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83/6 MI GP IMM - - XOR_IMM IMM_8
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83/0 MI GP IMM - - ADD_IMM IMM_8 LOCK
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83/1 MI GP IMM - - OR_IMM IMM_8 LOCK
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83/2 MI GP IMM - - ADC_IMM IMM_8 LOCK
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83/3 MI GP IMM - - SBB_IMM IMM_8 LOCK
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83/4 MI GP IMM - - AND_IMM IMM_8 LOCK
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83/5 MI GP IMM - - SUB_IMM IMM_8 LOCK
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83/6 MI GP IMM - - XOR_IMM IMM_8 LOCK
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83/7 MI GP IMM - - CMP_IMM IMM_8
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84 MR GP GP - - TEST SIZE_8
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85 MR GP GP - - TEST
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86 MR GP GP - - XCHG SIZE_8
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87 MR GP GP - - XCHG
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86 MR GP GP - - XCHG SIZE_8 LOCK
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87 MR GP GP - - XCHG LOCK
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88 MR GP GP - - MOV SIZE_8
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89 MR GP GP - - MOV
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8a RM GP GP - - MOV SIZE_8
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@@ -265,15 +265,15 @@ ef NP - - - - OUT INSTR_WIDTH
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f4 NP - - - - HLT
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f5 NP - - - - CMC
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f6/0 MI GP IMM - - TEST_IMM SIZE_8 IMM_8
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f6/2 M GP - - - NOT SIZE_8
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f6/3 M GP - - - NEG SIZE_8
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f6/2 M GP - - - NOT SIZE_8 LOCK
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f6/3 M GP - - - NEG SIZE_8 LOCK
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f6/4 M GP - - - MUL SIZE_8
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f6/5 M GP - - - IMUL SIZE_8
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f6/6 M GP - - - DIV SIZE_8
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f6/7 M GP - - - IDIV SIZE_8
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f7/0 MI GP IMM - - TEST_IMM
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f7/2 M GP - - - NOT
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f7/3 M GP - - - NEG
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f7/2 M GP - - - NOT LOCK
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f7/3 M GP - - - NEG LOCK
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f7/4 M GP - - - MUL
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f7/5 M GP - - - IMUL
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f7/6 M GP - - - DIV
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@@ -284,10 +284,10 @@ fa NP - - - - CLI
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fb NP - - - - STI
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fc NP - - - - CLD
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fd NP - - - - STD
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fe/0 M GP - - - INC SIZE_8
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fe/1 M GP - - - DEC SIZE_8
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ff/0 M GP - - - INC
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ff/1 M GP - - - DEC
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fe/0 M GP - - - INC SIZE_8 LOCK
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fe/1 M GP - - - DEC SIZE_8 LOCK
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ff/0 M GP - - - INC LOCK
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ff/1 M GP - - - DEC LOCK
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ff/2 M GP - - - CALL_IND DEF64
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#ff/3 CALLf TODO
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ff/4 M GP - - - JMP_IND DEF64
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@@ -399,30 +399,30 @@ ff/6 M GP - - - PUSH DEF64
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0fa8 NP - - - - PUSH_GS DEF64 INSTR_WIDTH
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0fa9 NP - - - - POP_GS DEF64 INSTR_WIDTH
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# 0faa RSM
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0fab MR GP GP - - BTS
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0fab MR GP GP - - BTS LOCK
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0fac MRI GP GP IMM8 - SHRD_IMM IMM_8
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0fad MR GP GP - - SHRD_CL
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0faf RM GP GP - - IMUL2
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0fb0 MR GP GP - - CMPXCHG SIZE_8
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0fb1 MR GP GP - - CMPXCHG
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0fb3 MR GP GP - - BTR
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0fb0 MR GP GP - - CMPXCHG SIZE_8 LOCK
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0fb1 MR GP GP - - CMPXCHG LOCK
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0fb3 MR GP GP - - BTR LOCK
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0fb6 RM GP GP8 - - MOVZX
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0fb7 RM GP GP16 - - MOVZX
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F3.0fb8 RM GP GP - - POPCNT
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0fb9 RM GP GP - - UD1
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0fba/4 MI GP IMM8 - - BT_IMM IMM_8
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0fba/5 MI GP IMM8 - - BTS_IMM IMM_8
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0fba/6 MI GP IMM8 - - BTR_IMM IMM_8
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0fba/7 MI GP IMM8 - - BTC_IMM IMM_8
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0fbb MR GP GP - - BTC
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0fba/5 MI GP IMM8 - - BTS_IMM IMM_8 LOCK
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0fba/6 MI GP IMM8 - - BTR_IMM IMM_8 LOCK
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0fba/7 MI GP IMM8 - - BTC_IMM IMM_8 LOCK
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0fbb MR GP GP - - BTC LOCK
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0fbc RM GP GP - - BSF_TZCNT
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0fbd RM GP GP - - BSR_LZCNT
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0fbe RM GP GP8 - - MOVSX
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0fbf RM GP GP16 - - MOVSX
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0fc0 MR GP GP - - XADD SIZE_8
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0fc1 MR GP GP - - XADD
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0fc0 MR GP GP - - XADD SIZE_8 LOCK
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0fc1 MR GP GP - - XADD LOCK
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NP.0fc3 MR GP GP - - MOVNTI
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0fc7//1 M GP - - - CMPXCHGD
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0fc7//1 M GP - - - CMPXCHGD LOCK
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0fc8+ O GP - - - BSWAP
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0fff NP - - - - UD0
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#
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@@ -37,6 +37,7 @@ InstrFlags = bitstruct("InstrFlags", [
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"gp_size_def64:1",
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"gp_instr_width:1",
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"gp_fixed_operand_size:3",
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"lock:1",
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])
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assert InstrFlags._encode_size <= 32
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@@ -113,6 +114,7 @@ class InstrDesc(namedtuple("InstrDesc", "mnemonic,flags,encoding")):
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if "SIZE_8" in desc[6:]: flags.gp_size_8 = 1
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if "INSTR_WIDTH" in desc[6:]: flags.gp_instr_width = 1
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if "IMM_8" in desc[6:]: flags.imm_byte = 1
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if "LOCK" in desc[6:]: flags.lock = 1
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return cls(desc[5], frozenset(desc[6:]), flags._encode())
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def encode(self, mnemonics_lut):
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