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instrs: Remove incorrect NFx specifiers

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The new trie implementation is more flexible and allows omitting
prefixes even with a ModRM specifier in the opcode. Use this flexibility
to simplify instruction descriptions.
This commit is contained in:
Alexis Engelke
2021-01-23 13:20:57 +01:00
parent dc399390a4
commit 85fdaa3a9b
3 changed files with 30 additions and 19 deletions
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33
instrs.txt
View File

@@ -315,16 +315,16 @@ ff/6 M GP - - - PUSH DEF64
0f00/3 M GP16 - - - LTR
0f00/4 M GP16 - - - VERR
0f00/5 M GP16 - - - VERW
NFx.0f01/0m M MEMZ - - - SGDT
NFx.0f01/1m M MEMZ - - - SIDT
NFx.0f01/2m M MEMZ - - - LGDT
NFx.0f01/3m M MEMZ - - - LIDT
NFx.0f01/4m M GP16 - - - SMSW
NFx.0f01/4r M GP - - - SMSW
NFx.0f01/6 M GP16 - - - LMSW
NFx.0f01/7m M GP - - - INVLPG SIZE_8
NFx.0f01c8 NP - - - - MONITOR
NFx.0f01c9 NP - - - - MWAIT
0f01/0m M MEMZ - - - SGDT
0f01/1m M MEMZ - - - SIDT
0f01/2m M MEMZ - - - LGDT
0f01/3m M MEMZ - - - LIDT
0f01/4m M GP16 - - - SMSW
0f01/4r M GP - - - SMSW
0f01/6 M GP16 - - - LMSW
0f01/7m M GP - - - INVLPG SIZE_8
0f01c8 NP - - - - MONITOR
0f01c9 NP - - - - MWAIT
NP.0f01ca NP - - - - CLAC
NP.0f01cb NP - - - - STAC
NP.0f01cf NP - - - - ENCLS
@@ -333,16 +333,15 @@ NP.0f01d1 NP - - - - XSETBV
NP.0f01d5 NP - - - - XEND
NP.0f01d6 NP - - - - XTEST
NP.0f01d7 NP - - - - ENCLU
NFx.0f01f8 NP - - - - SWAPGS ONLY64
NFx.0f01f9 NP - - - - RDTSCP
0f01f8 NP - - - - SWAPGS ONLY64
0f01f9 NP - - - - RDTSCP
0f02 RM GP GP16 - - LAR
0f03 RM GP GP16 - - LSL
0f05 NP - - - - SYSCALL ONLY64
0f06 NP - - - - CLTS
0f07 NP - - - - SYSRET ONLY64
0f08 NP - - - - INVD
NFx.0f09 NP - - - - WBINVD
F2.0f09 NP - - - - WBINVD
*0f09 NP - - - - WBINVD
0f0b NP - - - - UD2
0f0d/0m M MEM8 - - - PREFETCH
0f0d/1m M MEM8 - - - PREFETCHW
@@ -456,11 +455,9 @@ F3.0fb8 RM GP GP - - POPCNT USE66
0fba/6 MI GP IMM8 - - BTR LOCK
0fba/7 MI GP IMM8 - - BTC LOCK
0fbb MR GP GP - - BTC LOCK
NFx.0fbc RM GP GP - - BSF
F2.0fbc RM GP GP - - BSF USE66
*0fbc RM GP GP - - BSF
F3.0fbc RM GP GP - - TZCNT USE66
NFx.0fbd RM GP GP - - BSR
F2.0fbd RM GP GP - - BSR USE66
*0fbd RM GP GP - - BSR
F3.0fbd RM GP GP - - LZCNT USE66
0fbe RM GP GP8 - - MOVSX ENC_SEPSZ
0fbf RM GP GP16 - - MOVSX ENC_SEPSZ

2
parseinstrs.py
View File

@@ -440,7 +440,7 @@ def encode_table(entries):
mnemonics = defaultdict(list)
mnemonics["FE_NOP"].append(("NP", 0, 0, "0x90"))
for weak, opcode, desc in entries:
if weak or "ONLY32" in desc.flags:
if "ONLY32" in desc.flags or desc.mnemonic[:9] == "RESERVED_":
continue
opsizes = {8} if "SIZE_8" in desc.flags else {16, 32, 64}

14
tests/test_decode.c
View File

@@ -170,6 +170,20 @@ main(int argc, char** argv)
// [reg+s*reg+disp32]
TEST64("\x42\x01\x84\x25\x01\x00\x00\x00", "add dword ptr [rbp+1*r12+0x1], eax");
TEST("\x0f\xbc\xc0", "bsf eax, eax");
TEST("\x66\x0f\xbc\xc0", "bsf ax, ax");
TEST("\xf2\x0f\xbc\xc0", "bsf eax, eax");
TEST("\x66\xf2\x0f\xbc\xc0", "bsf ax, ax");
TEST("\xf3\x0f\xbc\xc0", "tzcnt eax, eax");
TEST("\x66\xf3\x0f\xbc\xc0", "tzcnt ax, ax");
TEST32("\x0f\x01\x00", "sgdt [eax]");
TEST64("\x0f\x01\x00", "sgdt [rax]");
TEST32("\x66\x0f\x01\x00", "sgdt [eax]");
TEST64("\x66\x0f\x01\x00", "sgdt [rax]");
TEST32("\xf2\x0f\x01\x00", "sgdt [eax]");
TEST64("\xf2\x0f\x01\x00", "sgdt [rax]");
TEST32("\xf3\x0f\x01\x00", "sgdt [eax]");
TEST64("\xf3\x0f\x01\x00", "sgdt [rax]");
TEST("\x04\x01", "add al, 0x1");
TEST("\x66\x68\xff\xad", "pushw 0xadff");
TEST32("\x68\xff\xad\x90\xbc", "push 0xbc90adff");