encode2: Add new encoder API, one func per instr.
This is an *experimental* (read: unstable) API which exposes encoding functionality as one function per instruction. This makes the encoding process itself significantly faster, at the cost of a much larger binary size (~1 MiB of code, no data) and much higher compilation time.
This commit is contained in:
Alexis Engelke
283
parseinstrs.py
283
parseinstrs.py
@@ -687,10 +687,293 @@ def encode_table(entries, args):
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mnem_tab = "".join(f"FE_MNEMONIC({m},{i})\n" for i, m in enumerate(mnem_list))
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return mnem_tab, descs
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def encode2_table(entries, args):
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mnemonics = defaultdict(list)
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for weak, opcode, desc in entries:
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if "I64" in desc.flags or desc.mnemonic[:9] == "RESERVED_":
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continue
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opsizes = {8} if "SZ8" in desc.flags else {16, 32, 64}
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hasvex, vecsizes = False, {128}
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if opcode.vex:
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hasvex, vecsizes = True, {128, 256}
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if opcode.prefix in ("66", "F2", "F3") and "U66" not in desc.flags:
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opsizes -= {16}
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if opcode.vexl == "IG":
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vecsizes = {0}
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elif opcode.vexl:
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vecsizes -= {128 if opcode.vexl == "1" else 256}
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if opcode.rexw == "IG":
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opsizes = {0}
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elif opcode.rexw:
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opsizes -= {32 if opcode.rexw == "1" else 64}
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if "I66" in desc.flags:
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opsizes -= {16}
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if "D64" in desc.flags:
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opsizes -= {32}
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if "SZ8" not in desc.flags and "INSTR_WIDTH" not in desc.flags and all(op.size != OpKind.SZ_OP for op in desc.operands):
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opsizes = {0}
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if "VSIB" not in desc.flags and all(op.size != OpKind.SZ_VEC for op in desc.operands):
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vecsizes = {0} # for VEX-encoded general-purpose instructions.
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if "ENC_NOSZ" in desc.flags:
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opsizes, vecsizes = {0}, {0}
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# Where to put the operand size in the mnemonic
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separate_opsize = "ENC_SEPSZ" in desc.flags
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prepend_opsize = max(opsizes) > 0 and not separate_opsize
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prepend_vecsize = hasvex and max(vecsizes) > 0 and not separate_opsize
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if "F64" in desc.flags:
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opsizes = {64}
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prepend_opsize = False
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modrm_type = opcode.modreg[1] if opcode.modreg else "rm"
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optypes_base = desc.optype_str()
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optypes = {optypes_base.replace("M", t) for t in modrm_type}
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prefixes = [("", "")]
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if "LOCK" in desc.flags:
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prefixes.append(("LOCK_", "LOCK"))
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if "ENC_REP" in desc.flags:
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prefixes.append(("REP_", "F3"))
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if "ENC_REPCC" in desc.flags:
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prefixes.append(("REPNZ_", "F2"))
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prefixes.append(("REPZ_", "F3"))
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for opsize, vecsize, prefix, ots in product(opsizes, vecsizes, prefixes, optypes):
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if prefix[1] == "LOCK" and ots[0] != "m":
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continue
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spec_opcode = opcode
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if prefix[1]:
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spec_opcode = spec_opcode._replace(prefix=prefix[1])
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if opsize == 64 and "D64" not in desc.flags and "F64" not in desc.flags:
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spec_opcode = spec_opcode._replace(rexw="1")
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if vecsize == 256:
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spec_opcode = spec_opcode._replace(vexl="1")
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# Construct mnemonic name
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mnem_name = {"MOVABS": "MOV", "XCHG_NOP": "XCHG"}.get(desc.mnemonic, desc.mnemonic)
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name = prefix[0] + mnem_name
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if prepend_opsize and not ("D64" in desc.flags and opsize == 64):
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name += f"_{opsize}"[name[-1] not in "0123456789":]
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if prepend_vecsize:
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name += f"_{vecsize}"[name[-1] not in "0123456789":]
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for ot, op in zip(ots, desc.operands):
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name += ot.replace("o", "")
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if separate_opsize:
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name += f"{op.abssize(opsize//8, vecsize//8)*8}"
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mnemonics[name, opsize, ots].append((spec_opcode, desc))
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enc_decls, enc_code = "", ""
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for (mnem, opsize, ots), variants in mnemonics.items():
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dedup = OrderedDict()
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for i, (opcode, desc) in enumerate(variants):
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PRIO = ["O", "OA", "AO", "AM", "MA", "IA", "OI"]
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enc_prio = PRIO.index(desc.encoding) if desc.encoding in PRIO else len(PRIO)
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unique = 0 if desc.encoding != "S" else i
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key = desc.imm_size(opsize//8), enc_prio, unique
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if key not in dedup:
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dedup[key] = opcode, desc
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if desc.encoding == "S":
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print(mnem, key, desc, dedup)
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variants = [dedup[k] for k in sorted(dedup.keys())]
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max_imm_size = max(k[0] for k in dedup.keys())
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supports_high_regs = []
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if variants[0][1].mnemonic in ("MOVSX", "MOVZX") or opsize == 8:
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# Should be the same for all variants
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desc = variants[0][1]
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for i, (ot, op) in enumerate(zip(ots, desc.operands)):
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if ot == "r" and op.kind == "GP" and op.abssize(opsize//8) == 1:
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supports_high_regs.append(i)
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supports_vsib = "VSIB" in variants[0][1].flags
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if len({tuple(op.kind for op in v[1].operands) for v in variants}) > 1:
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raise Exception(f"ambiguous operand kinds for {mnem}")
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OPKIND_LUT = {"FPU": "ST", "SEG": "SREG", "MMX": "MM"}
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reg_tys = [OPKIND_LUT.get(op.kind, op.kind) for op in variants[0][1].operands]
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fnname = f"fe64_{mnem}{'_impl' if supports_high_regs else ''}"
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op_tys = [{
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"i": f"int{max_imm_size*8 if max_imm_size != 3 else 32}_t",
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"a": "uintptr_t",
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"r": f"FeReg{reg_ty if i not in supports_high_regs else 'GPLH'}",
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"m": "FeMem" if not supports_vsib else "FeMemV",
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"o": "const void*",
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}[ot] for i, (ot, reg_ty) in enumerate(zip(ots, reg_tys))]
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fn_opargs = "".join(f", {ty} op{i}" for i, ty in enumerate(op_tys))
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fn_sig = f"unsigned {fnname}(uint8_t* buf, int flags{fn_opargs})"
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enc_decls += f"{fn_sig};\n"
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if supports_high_regs:
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enc_decls += f"#define fe64_{mnem}(buf, flags"
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enc_decls += "".join(f", op{i}" for i in range(len(op_tys)))
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enc_decls += f") {fnname}(buf, flags"
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enc_decls += "".join(f", FE_MAKE_GPLH(op{i})" if i in supports_high_regs else f", op{i}" for i in range(len(op_tys)))
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enc_decls += f")\n"
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code = f"{fn_sig} {{\n"
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code += " unsigned idx = 0, rex = 0, memoff;\n"
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if max_imm_size or "a" in ots:
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code += " int64_t imm; unsigned imm_size;\n"
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code += " (void) flags; (void) memoff;\n"
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neednext = True
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for i, (opcode, desc) in enumerate(variants):
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if not neednext:
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break
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if i > 0:
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code += f"\nnext{i-1}:\n"
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neednext = False
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imm_size = desc.imm_size(opsize//8)
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flags = ENCODINGS[desc.encoding]
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# Select usable encoding.
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if desc.encoding == "S":
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# Segment encoding is weird.
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code += f" if (op_reg_idx(op0)!={(opcode.opc>>3)&0x7:#x}) goto next{i};\n"
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neednext = True
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if desc.mnemonic == "XCHG_NOP" and opsize == 32:
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# XCHG eax, eax must not be encoded as 90 -- that'd be NOP.
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code += f" if (op_reg_idx(op0)==0&&op_reg_idx(op1)==0) goto next{i};\n"
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neednext = True
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if flags.zeroreg_idx:
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code += f" if (op_reg_idx(op{flags.zeroreg_idx^3})!={flags.zeroreg_val}) goto next{i};\n"
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neednext = True
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if flags.imm_control:
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if flags.imm_control != 3:
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code += f" imm = (int64_t) op{flags.imm_idx^3};\n"
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else:
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code += f" imm = op_reg_idx(op{flags.imm_idx^3}) << 4;\n"
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code += f" imm_size = {imm_size};\n"
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if flags.imm_control == 1:
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code += f" if (imm != 1) goto next{i};\n"
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neednext = True
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if flags.imm_control == 2:
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code += " imm_size = flags & FE_ADDR32 ? 4 : 8;\n"
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code += " if (imm_size == 4) imm = (int32_t) imm;\n"
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if imm_size < max_imm_size and 2 <= flags.imm_control < 6:
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code += f" if (!op_imm_n(imm, imm_size)) goto next{i};\n"
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neednext = True
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if flags.imm_control == 6:
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# idx is subtracted below.
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code += f" imm -= (int64_t) buf + imm_size;\n"
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if i != len(variants) - 1: # only Jcc+JMP
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code += f" if (flags&FE_JMPL) goto next{i};\n"
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# assume one-byte opcode without escape/prefixes
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code += f" if (!op_imm_n(imm-1, imm_size)) goto next{i};\n"
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neednext = True
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if opcode.vex:
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rexw, rexr, rexx, rexb = 0x8000, 0x80, 0x40, 0x20
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else:
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rexw, rexr, rexx, rexb = 0x48, 0x44, 0x42, 0x41
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if not opcode.vex:
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for i in supports_high_regs:
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code += f" if (op_reg_idx(op{i}) >= 4 && op_reg_idx(op{i}) <= 15) rex = 0x40;\n"
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if opcode.rexw == "1":
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code += f" rex |= {rexw:#x};\n"
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if flags.modrm_idx:
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ismem = ots[flags.modrm_idx^3] == "m"
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if ismem:
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code += f" if (op_mem_base(op{flags.modrm_idx^3})&8) rex |= {rexb:#x};\n"
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code += f" if (op_mem_idx(op{flags.modrm_idx^3})&8) rex |= {rexx:#x};\n"
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else:
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if desc.operands[flags.modrm_idx^3].kind in ("GP", "XMM"):
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code += f" if (op_reg_idx(op{flags.modrm_idx^3})&8) rex |= {rexb:#x};\n"
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if flags.modreg_idx:
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if desc.operands[flags.modreg_idx^3].kind in ("GP", "XMM", "CR", "DR"):
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code += f" if (op_reg_idx(op{flags.modreg_idx^3})&8) rex |= {rexr:#x};\n"
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elif flags.modreg_idx: # O encoding
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if desc.operands[flags.modreg_idx^3].kind in ("GP", "XMM"):
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code += f" if (op_reg_idx(op{flags.modreg_idx^3})&8) rex |= {rexb:#x};\n"
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for i in supports_high_regs:
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code += f" if (rex && op_reg_gph(op{i})) return 0;\n"
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if "m" in ots or "USEG" in desc.flags:
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code += " if (UNLIKELY(flags & FE_SEG_MASK)) buf[idx++] = enc_seg(flags);\n"
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if "m" in ots or "U67" in desc.flags:
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code += " if (UNLIKELY(flags & FE_ADDR32)) buf[idx++] = 0x67;\n"
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if opcode.vex:
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ppl = ["NP", "66", "F3", "F2"].index(opcode.prefix)
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ppl |= 4 if opcode.vexl == "1" else 0
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mayvex2 = opcode.rexw != "1" and opcode.escape == 1
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if mayvex2:
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code += " if (!(rex&0x8060)) {\n"
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code += " buf[idx++] = 0xc5;\n"
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code += " rex ^= 0x80;\n"
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code += " } else {\n"
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code += " buf[idx++] = 0xc4;\n"
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code += f" buf[idx++] = {0xe0+opcode.escape:#x}^rex;\n"
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code += " rex >>= 8;\n"
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if mayvex2:
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code += " }\n"
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vexop = 0
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if flags.vexreg_idx:
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vexop = f"op_reg_idx(op{flags.vexreg_idx^3})"
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code += f" buf[idx++] = {ppl}|rex|(({vexop}^15)<<3);\n"
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else:
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if opsize == 16 or opcode.prefix == "66":
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code += " buf[idx++] = 0x66;\n"
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if opcode.prefix in ("F2", "F3"):
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code += f" buf[idx++] = 0x{opcode.prefix};\n"
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if opcode.prefix == "LOCK":
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code += f" buf[idx++] = 0xF0;\n"
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code += f" if (rex) buf[idx++] = rex;\n"
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if opcode.escape:
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code += f" buf[idx++] = 0x0F;\n"
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if opcode.escape == 2:
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code += f" buf[idx++] = 0x38;\n"
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elif opcode.escape == 3:
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code += f" buf[idx++] = 0x3A;\n"
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code += f" buf[idx++] = {opcode.opc:#x};\n"
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if opcode.opcext:
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code += f" buf[idx++] = {opcode.opcext:#x};\n"
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if flags.modrm:
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modrm = f"op{flags.modrm_idx^3}"
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if flags.modreg_idx:
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modreg = f"op_reg_idx(op{flags.modreg_idx^3})"
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else:
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modreg = int(opcode.modreg[0]) if opcode.modreg else 0
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if ismem:
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imm_size_expr = "imm_size" if flags.imm_control >= 2 else 0
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memfn = "enc_mem_vsib" if "VSIB" in desc.flags else "enc_mem"
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code += f" memoff = {memfn}(buf, idx, {modrm}, {modreg}, {imm_size_expr}, 0);\n"
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code += f" if (!memoff) return 0;\n idx += memoff;\n"
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else:
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modrm = f"op_reg_idx({modrm})"
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code += f" buf[idx++] = 0xC0|(({modreg}&7)<<3)|({modrm}&7);\n"
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elif flags.modrm_idx:
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code += f" buf[idx-1] |= op_reg_idx(op{flags.modrm_idx^3}) & 7;\n"
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if flags.imm_control >= 2:
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if flags.imm_control == 6:
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code += f" imm -= idx;\n"
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code += f" if (enc_imm(buf+idx, imm, imm_size)) return 0;\n"
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code += f" idx += imm_size;\n"
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code += f" return idx;\n"
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if neednext:
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code += f"next{len(variants)-1}: return 0;\n"
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code += "}\n"
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enc_code += code
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return enc_decls, enc_code
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if __name__ == "__main__":
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generators = {
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"decode": decode_table,
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"encode": encode_table,
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"encode2": encode2_table,
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}
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parser = argparse.ArgumentParser()
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Block a user