commit 8e26fa9ec793fe925fd2a31fea3124acd5ae7168 Author: T0b1 Date: Fri Apr 28 20:41:36 2023 +0200 init diff --git a/.appveyor.yml b/.appveyor.yml new file mode 100644 index 0000000..50910bd --- /dev/null +++ b/.appveyor.yml @@ -0,0 +1,11 @@ +install: + - appveyor-retry appveyor DownloadFile https://win.rustup.rs/ -FileName rustup-init.exe + - if not defined RUSTFLAGS rustup-init.exe -y --default-host x86_64-pc-windows-msvc --default-toolchain nightly + - set PATH=%PATH%;C:\Users\appveyor\.cargo\bin + - rustc -V + - cargo -V + +build: false + +test_script: + - cargo test --locked diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..4e30131 --- /dev/null +++ b/.gitignore @@ -0,0 +1,6 @@ +/target +**/*.rs.bk +Cargo.lock +bin/ +pkg/ +wasm-pack.log diff --git a/.gitmodules b/.gitmodules new file mode 100644 index 0000000..9d5a6ad --- /dev/null +++ b/.gitmodules @@ -0,0 +1,3 @@ +[submodule "extern/fadec"] + path = extern/fadec + url = https://github.com/aengelke/fadec.git diff --git a/.travis.yml b/.travis.yml new file mode 100644 index 0000000..7a91325 --- /dev/null +++ b/.travis.yml @@ -0,0 +1,69 @@ +language: rust +sudo: false + +cache: cargo + +matrix: + include: + + # Builds with wasm-pack. + - rust: beta + env: RUST_BACKTRACE=1 + addons: + firefox: latest + chrome: stable + before_script: + - (test -x $HOME/.cargo/bin/cargo-install-update || cargo install cargo-update) + - (test -x $HOME/.cargo/bin/cargo-generate || cargo install --vers "^0.2" cargo-generate) + - cargo install-update -a + - curl https://rustwasm.github.io/wasm-pack/installer/init.sh -sSf | sh -s -- -f + script: + - cargo generate --git . --name testing + # Having a broken Cargo.toml (in that it has curlies in fields) anywhere + # in any of our parent dirs is problematic. + - mv Cargo.toml Cargo.toml.tmpl + - cd testing + - wasm-pack build + - wasm-pack test --chrome --firefox --headless + + # Builds on nightly. + - rust: nightly + env: RUST_BACKTRACE=1 + before_script: + - (test -x $HOME/.cargo/bin/cargo-install-update || cargo install cargo-update) + - (test -x $HOME/.cargo/bin/cargo-generate || cargo install --vers "^0.2" cargo-generate) + - cargo install-update -a + - rustup target add wasm32-unknown-unknown + script: + - cargo generate --git . --name testing + - mv Cargo.toml Cargo.toml.tmpl + - cd testing + - cargo check + - cargo check --target wasm32-unknown-unknown + - cargo check --no-default-features + - cargo check --target wasm32-unknown-unknown --no-default-features + - cargo check --no-default-features --features console_error_panic_hook + - cargo check --target wasm32-unknown-unknown --no-default-features --features console_error_panic_hook + - cargo check --no-default-features --features "console_error_panic_hook wee_alloc" + - cargo check --target wasm32-unknown-unknown --no-default-features --features "console_error_panic_hook wee_alloc" + + # Builds on beta. + - rust: beta + env: RUST_BACKTRACE=1 + before_script: + - (test -x $HOME/.cargo/bin/cargo-install-update || cargo install cargo-update) + - (test -x $HOME/.cargo/bin/cargo-generate || cargo install --vers "^0.2" cargo-generate) + - cargo install-update -a + - rustup target add wasm32-unknown-unknown + script: + - cargo generate --git . --name testing + - mv Cargo.toml Cargo.toml.tmpl + - cd testing + - cargo check + - cargo check --target wasm32-unknown-unknown + - cargo check --no-default-features + - cargo check --target wasm32-unknown-unknown --no-default-features + - cargo check --no-default-features --features console_error_panic_hook + - cargo check --target wasm32-unknown-unknown --no-default-features --features console_error_panic_hook + # Note: no enabling the `wee_alloc` feature here because it requires + # nightly for now. diff --git a/Cargo.toml b/Cargo.toml new file mode 100644 index 0000000..a674bc7 --- /dev/null +++ b/Cargo.toml @@ -0,0 +1,38 @@ +[package] +name = "rust-as" +version = "0.1.0" +authors = ["T0b1 "] +edition = "2018" + +[lib] +crate-type = ["cdylib", "rlib"] + +[features] +default = ["console_error_panic_hook"] + +[dependencies] +wasm-bindgen = "0.2.63" + +# The `console_error_panic_hook` crate provides better debugging of panics by +# logging them with `console.error`. This is great for development, but requires +# all the `std::fmt` and `std::panicking` infrastructure, so isn't great for +# code size when deploying. +console_error_panic_hook = { version = "0.1.6", optional = true } + +# `wee_alloc` is a tiny allocator for wasm that is only ~1K in code size +# compared to the default allocator's ~10K. It is slower than the default +# allocator, however. +wee_alloc = { version = "0.4.5", optional = true } + +phf = { version = "0.11", features = ["macros"] } + +[build-dependencies] +meson-next = "1.2.2" +bindgen = "0.65.1" + +[dev-dependencies] +wasm-bindgen-test = "0.3.13" + +[profile.release] +# Tell `rustc` to optimize for small code size. +opt-level = "s" diff --git a/LICENSE_APACHE b/LICENSE_APACHE new file mode 100644 index 0000000..11069ed --- /dev/null +++ b/LICENSE_APACHE @@ -0,0 +1,201 @@ + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + +TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + +1. 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However, in accepting such obligations, You may act only + on Your own behalf and on Your sole responsibility, not on behalf + of any other Contributor, and only if You agree to indemnify, + defend, and hold each Contributor harmless for any liability + incurred by, or claims asserted against, such Contributor by reason + of your accepting any such warranty or additional liability. + +END OF TERMS AND CONDITIONS + +APPENDIX: How to apply the Apache License to your work. + + To apply the Apache License to your work, attach the following + boilerplate notice, with the fields enclosed by brackets "[]" + replaced with your own identifying information. (Don't include + the brackets!) The text should be enclosed in the appropriate + comment syntax for the file format. We also recommend that a + file or class name and description of purpose be included on the + same "printed page" as the copyright notice for easier + identification within third-party archives. + +Copyright [yyyy] [name of copyright owner] + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. diff --git a/LICENSE_MIT b/LICENSE_MIT new file mode 100644 index 0000000..383aaa0 --- /dev/null +++ b/LICENSE_MIT @@ -0,0 +1,25 @@ +Copyright (c) 2018 T0b1 + +Permission is hereby granted, free of charge, to any +person obtaining a copy of this software and associated +documentation files (the "Software"), to deal in the +Software without restriction, including without +limitation the rights to use, copy, modify, merge, +publish, distribute, sublicense, and/or sell copies of +the Software, and to permit persons to whom the Software +is furnished to do so, subject to the following +conditions: + +The above copyright notice and this permission notice +shall be included in all copies or substantial portions +of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF +ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A +PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT +SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR +IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +DEALINGS IN THE SOFTWARE. diff --git a/README.md b/README.md new file mode 100644 index 0000000..be29ebd --- /dev/null +++ b/README.md @@ -0,0 +1,86 @@ +
+ +

wasm-pack-template

+ + A template for kick starting a Rust and WebAssembly project using wasm-pack. + +

+ Build Status +

+ +

+ Tutorial + | + Chat +

+ + Built with 🦀🕸 by The Rust and WebAssembly Working Group +
+ +## About + +[**📚 Read this template tutorial! 📚**][template-docs] + +This template is designed for compiling Rust libraries into WebAssembly and +publishing the resulting package to NPM. + +Be sure to check out [other `wasm-pack` tutorials online][tutorials] for other +templates and usages of `wasm-pack`. + +[tutorials]: https://rustwasm.github.io/docs/wasm-pack/tutorials/index.html +[template-docs]: https://rustwasm.github.io/docs/wasm-pack/tutorials/npm-browser-packages/index.html + +## 🚴 Usage + +### 🐑 Use `cargo generate` to Clone this Template + +[Learn more about `cargo generate` here.](https://github.com/ashleygwilliams/cargo-generate) + +``` +cargo generate --git https://github.com/rustwasm/wasm-pack-template.git --name my-project +cd my-project +``` + +### 🛠️ Build with `wasm-pack build` + +``` +wasm-pack build +``` + +### 🔬 Test in Headless Browsers with `wasm-pack test` + +``` +wasm-pack test --headless --firefox +``` + +### 🎁 Publish to NPM with `wasm-pack publish` + +``` +wasm-pack publish +``` + +## 🔋 Batteries Included + +* [`wasm-bindgen`](https://github.com/rustwasm/wasm-bindgen) for communicating + between WebAssembly and JavaScript. +* [`console_error_panic_hook`](https://github.com/rustwasm/console_error_panic_hook) + for logging panic messages to the developer console. +* [`wee_alloc`](https://github.com/rustwasm/wee_alloc), an allocator optimized + for small code size. +* `LICENSE-APACHE` and `LICENSE-MIT`: most Rust projects are licensed this way, so these are included for you + +## License + +Licensed under either of + +* Apache License, Version 2.0, ([LICENSE-APACHE](LICENSE-APACHE) or http://www.apache.org/licenses/LICENSE-2.0) +* MIT license ([LICENSE-MIT](LICENSE-MIT) or http://opensource.org/licenses/MIT) + +at your option. + +### Contribution + +Unless you explicitly state otherwise, any contribution intentionally +submitted for inclusion in the work by you, as defined in the Apache-2.0 +license, shall be dual licensed as above, without any additional terms or +conditions. \ No newline at end of file diff --git a/build.rs b/build.rs new file mode 100644 index 0000000..a9ff9c0 --- /dev/null +++ b/build.rs @@ -0,0 +1,92 @@ +use std::collections::HashMap; +use std::env; +use std::path::PathBuf; + +#[derive(Debug)] +struct ParseCallback(); + +impl bindgen::callbacks::ParseCallbacks for ParseCallback { + fn enum_variant_name( + &self, + enum_name: Option<&str>, + original_variant_name: &str, + _variant_value: bindgen::callbacks::EnumVariantValue, + ) -> Option { + if let Some(name) = enum_name { + if name == "FeReg" { + return Some(original_variant_name.strip_prefix("FE_").unwrap_or(original_variant_name).to_owned()); + } + } + + None + } + + fn will_parse_macro(&self, name: &str) -> bindgen::callbacks::MacroParsingBehavior { + if name == "FE_ADDR32" || name == "FE_NOREG" || name == "FE_JMPL" { + return bindgen::callbacks::MacroParsingBehavior::Default; + } + + if name.starts_with("FE_") { + // prevent instructions from being parsed + return bindgen::callbacks::MacroParsingBehavior::Ignore; + } + + return bindgen::callbacks::MacroParsingBehavior::Default; + } +} + + + +fn main() { + let build_path = PathBuf::from(env::var("OUT_DIR").unwrap()).join("fadec-build"); + let build_path = build_path.to_str().unwrap(); + + // build faenc + { + let mut config = HashMap::new(); + config.insert("wasm_build", "true"); + let config = meson_next::config::Config::new().options(config); + + println!("cargo:rustc-link-lib=fadec"); + println!("cargo:rustc-link-search=native={}", build_path); + meson_next::build("extern/fadec", build_path, config); + } + + // Tell cargo to invalidate the built crate whenever the wrapper changes + println!("cargo:rerun-if-changed=extern/fadec"); + + // The bindgen::Builder is the main entry point + // to bindgen, and lets you build up options for + // the resulting bindings. + let bindings = bindgen::Builder::default() + // The input header we would like to generate + // bindings for. + .header("extern/fadec/fadec-enc.h") + .clang_arg(&format!("-I{}", build_path)) + .rustified_enum("FeReg") + .parse_callbacks(Box::new(ParseCallback())) + // Tell cargo to invalidate the built crate whenever any of the + // included header files changed. + .parse_callbacks(Box::new(bindgen::CargoCallbacks)) + // Finish the builder and generate the bindings. + .generate() + // Unwrap the Result and panic on failure. + .expect("Unable to generate bindings"); + + // Write the bindings to the $OUT_DIR/bindings.rs file. + let out_path = PathBuf::from(env::var("OUT_DIR").unwrap()); + bindings + .write_to_file(out_path.join("bindings.rs")) + .expect("Couldn't write bindings!"); + + // you wouldn't expect it but bindgen refuses to parse a file that does not end with '.h' + // lmao + std::fs::copy(format!("{}/fadec-encode-public.inc", build_path), format!("{}/fadec-encode-public.h", build_path)).expect("copy failed"); + + let inst_bindings = bindgen::Builder::default() + .header(format!("{}/fadec-encode-public.h", build_path)) + .generate() + .expect("Unable to generate bindings"); + + inst_bindings.write_to_file(out_path.join("inst_bindings.rs")).expect("Couldn't write inst_bindings!"); +} \ No newline at end of file diff --git a/extern/fadec b/extern/fadec new file mode 160000 index 0000000..9263c3d --- /dev/null +++ b/extern/fadec @@ -0,0 +1 @@ +Subproject commit 9263c3d6b2b6142a1ab3958e2edc5de385d329c0 diff --git a/fadec-encode-public.h b/fadec-encode-public.h new file mode 100644 index 0000000..231b60f --- /dev/null +++ b/fadec-encode-public.h @@ -0,0 +1,3523 @@ +#define FE_ADD8mr 0x30400000000000 +#define FE_ADD8rr 0x30600000000000 +#define FE_LOCK_ADD8mr 0x30400000800000 +#define FE_ADD16mr 0x30000000080001 +#define FE_ADD16rr 0x30000000080001 +#define FE_LOCK_ADD16mr 0x30000000880001 +#define FE_ADD32mr 0x30000000000001 +#define FE_ADD32rr 0x30000000000001 +#define FE_LOCK_ADD32mr 0x30000000800001 +#define FE_ADD64mr 0x30000000400001 +#define FE_ADD64rr 0x30000000400001 +#define FE_LOCK_ADD64mr 0x30000000c00001 +#define FE_ADD8rm 0x38200000000002 +#define FE_ADD16rm 0x38000000080003 +#define FE_ADD32rm 0x38000000000003 +#define FE_ADD64rm 0x38000000400003 +#define FE_ADD8ri 0x178a00000000004 +#define FE_ADD16ri 0x220800000080083 +#define FE_ADD32ri 0x420800000000083 +#define FE_ADD64ri 0x620800000400083 +#define FE_OR8mr 0x30400000000008 +#define FE_OR8rr 0x30600000000008 +#define FE_LOCK_OR8mr 0x30400000800008 +#define FE_OR16mr 0x30000000080009 +#define FE_OR16rr 0x30000000080009 +#define FE_LOCK_OR16mr 0x30000000880009 +#define FE_OR32mr 0x30000000000009 +#define FE_OR32rr 0x30000000000009 +#define FE_LOCK_OR32mr 0x30000000800009 +#define FE_OR64mr 0x30000000400009 +#define FE_OR64rr 0x30000000400009 +#define FE_LOCK_OR64mr 0x30000000c00009 +#define FE_OR8rm 0x3820000000000a +#define FE_OR16rm 0x3800000008000b +#define FE_OR32rm 0x3800000000000b +#define FE_OR64rm 0x3800000040000b +#define FE_OR8ri 0x878a0000000000c +#define FE_OR16ri 0x920800000080183 +#define FE_OR32ri 0xb20800000000183 +#define FE_OR64ri 0xd20800000400183 +#define FE_ADC8mr 0x30400000000010 +#define FE_ADC8rr 0x30600000000010 +#define FE_LOCK_ADC8mr 0x30400000800010 +#define FE_ADC16mr 0x30000000080011 +#define FE_ADC16rr 0x30000000080011 +#define FE_LOCK_ADC16mr 0x30000000880011 +#define FE_ADC32mr 0x30000000000011 +#define FE_ADC32rr 0x30000000000011 +#define FE_LOCK_ADC32mr 0x30000000800011 +#define FE_ADC64mr 0x30000000400011 +#define FE_ADC64rr 0x30000000400011 +#define FE_LOCK_ADC64mr 0x30000000c00011 +#define FE_ADC8rm 0x38200000000012 +#define FE_ADC16rm 0x38000000080013 +#define FE_ADC32rm 0x38000000000013 +#define FE_ADC64rm 0x38000000400013 +#define FE_ADC8ri 0xf78a00000000014 +#define FE_ADC16ri 0x1020800000080283 +#define FE_ADC32ri 0x1220800000000283 +#define FE_ADC64ri 0x1420800000400283 +#define FE_SBB8mr 0x30400000000018 +#define FE_SBB8rr 0x30600000000018 +#define FE_LOCK_SBB8mr 0x30400000800018 +#define FE_SBB16mr 0x30000000080019 +#define FE_SBB16rr 0x30000000080019 +#define FE_LOCK_SBB16mr 0x30000000880019 +#define FE_SBB32mr 0x30000000000019 +#define FE_SBB32rr 0x30000000000019 +#define FE_LOCK_SBB32mr 0x30000000800019 +#define FE_SBB64mr 0x30000000400019 +#define FE_SBB64rr 0x30000000400019 +#define FE_LOCK_SBB64mr 0x30000000c00019 +#define FE_SBB8rm 0x3820000000001a +#define FE_SBB16rm 0x3800000008001b +#define FE_SBB32rm 0x3800000000001b +#define FE_SBB64rm 0x3800000040001b +#define FE_SBB8ri 0x1678a0000000001c +#define FE_SBB16ri 0x1720800000080383 +#define FE_SBB32ri 0x1920800000000383 +#define FE_SBB64ri 0x1b20800000400383 +#define FE_AND8mr 0x30400000000020 +#define FE_AND8rr 0x30600000000020 +#define FE_LOCK_AND8mr 0x30400000800020 +#define FE_AND16mr 0x30000000080021 +#define FE_AND16rr 0x30000000080021 +#define FE_LOCK_AND16mr 0x30000000880021 +#define FE_AND32mr 0x30000000000021 +#define FE_AND32rr 0x30000000000021 +#define FE_LOCK_AND32mr 0x30000000800021 +#define FE_AND64mr 0x30000000400021 +#define FE_AND64rr 0x30000000400021 +#define FE_LOCK_AND64mr 0x30000000c00021 +#define FE_AND8rm 0x38200000000022 +#define FE_AND16rm 0x38000000080023 +#define FE_AND32rm 0x38000000000023 +#define FE_AND64rm 0x38000000400023 +#define FE_AND8ri 0x1d78a00000000024 +#define FE_AND16ri 0x1e20800000080483 +#define FE_AND32ri 0x2020800000000483 +#define FE_AND64ri 0x2220800000400483 +#define FE_SUB8mr 0x30400000000028 +#define FE_SUB8rr 0x30600000000028 +#define FE_LOCK_SUB8mr 0x30400000800028 +#define FE_SUB16mr 0x30000000080029 +#define FE_SUB16rr 0x30000000080029 +#define FE_LOCK_SUB16mr 0x30000000880029 +#define FE_SUB32mr 0x30000000000029 +#define FE_SUB32rr 0x30000000000029 +#define FE_LOCK_SUB32mr 0x30000000800029 +#define FE_SUB64mr 0x30000000400029 +#define FE_SUB64rr 0x30000000400029 +#define FE_LOCK_SUB64mr 0x30000000c00029 +#define FE_SUB8rm 0x3820000000002a +#define FE_SUB16rm 0x3800000008002b +#define FE_SUB32rm 0x3800000000002b +#define FE_SUB64rm 0x3800000040002b +#define FE_SUB8ri 0x2478a0000000002c +#define FE_SUB16ri 0x2520800000080583 +#define FE_SUB32ri 0x2720800000000583 +#define FE_SUB64ri 0x2920800000400583 +#define FE_XOR8mr 0x30400000000030 +#define FE_XOR8rr 0x30600000000030 +#define FE_LOCK_XOR8mr 0x30400000800030 +#define FE_XOR16mr 0x30000000080031 +#define FE_XOR16rr 0x30000000080031 +#define FE_LOCK_XOR16mr 0x30000000880031 +#define FE_XOR32mr 0x30000000000031 +#define FE_XOR32rr 0x30000000000031 +#define FE_LOCK_XOR32mr 0x30000000800031 +#define FE_XOR64mr 0x30000000400031 +#define FE_XOR64rr 0x30000000400031 +#define FE_LOCK_XOR64mr 0x30000000c00031 +#define FE_XOR8rm 0x38200000000032 +#define FE_XOR16rm 0x38000000080033 +#define FE_XOR32rm 0x38000000000033 +#define FE_XOR64rm 0x38000000400033 +#define FE_XOR8ri 0x2b78a00000000034 +#define FE_XOR16ri 0x2c20800000080683 +#define FE_XOR32ri 0x2e20800000000683 +#define FE_XOR64ri 0x3020800000400683 +#define FE_CMP8mr 0x30400000000038 +#define FE_CMP8rr 0x30600000000038 +#define FE_CMP16mr 0x30000000080039 +#define FE_CMP16rr 0x30000000080039 +#define FE_CMP32mr 0x30000000000039 +#define FE_CMP32rr 0x30000000000039 +#define FE_CMP64mr 0x30000000400039 +#define FE_CMP64rr 0x30000000400039 +#define FE_CMP8rm 0x3820000000003a +#define FE_CMP16rm 0x3800000008003b +#define FE_CMP32rm 0x3800000000003b +#define FE_CMP64rm 0x3800000040003b +#define FE_CMP8ri 0x3278a0000000003c +#define FE_CMP16ri 0x3320800000080783 +#define FE_CMP32ri 0x3520800000000783 +#define FE_CMP64ri 0x3720800000400783 +#define FE_PUSH16r 0x3980000000080050 +#define FE_PUSHr 0x3a80000000000050 +#define FE_POP16r 0x3b80000000080058 +#define FE_POPr 0x3c80000000000058 +#define FE_MOVSXr16m32 0x38000000080063 +#define FE_MOVSXr16r32 0x38000000080063 +#define FE_MOVSXr32m32 0x38000000000063 +#define FE_MOVSXr32r32 0x38000000000063 +#define FE_MOVSXr64m32 0x38000000400063 +#define FE_MOVSXr64r32 0x38000000400063 +#define FE_PUSH16i 0x3d7080000008006a +#define FE_PUSHi 0x3e7080000000006a +#define FE_IMUL16rmi 0x3f5080000008006b +#define FE_IMUL16rri 0x405080000008006b +#define FE_IMUL32rmi 0x415080000000006b +#define FE_IMUL32rri 0x425080000000006b +#define FE_IMUL64rmi 0x435080000040006b +#define FE_IMUL64rri 0x445080000040006b +#define FE_INS8 0x800000000006c +#define FE_REP_INS8 0x800000020006c +#define FE_INS16 0x800000008006d +#define FE_REP_INS16 0x800000028006d +#define FE_INS32 0x800000000006d +#define FE_REP_INS32 0x800000020006d +#define FE_INS64 0x800000040006d +#define FE_REP_INS64 0x800000060006d +#define FE_OUTS8 0x800000000006e +#define FE_REP_OUTS8 0x800000020006e +#define FE_OUTS16 0x800000008006f +#define FE_REP_OUTS16 0x800000028006f +#define FE_OUTS32 0x800000000006f +#define FE_REP_OUTS32 0x800000020006f +#define FE_OUTS64 0x800000040006f +#define FE_REP_OUTS64 0x800000060006f +#define FE_JO 0x45a8800000000070 +#define FE_JNO 0x46a8800000000071 +#define FE_JC 0x47a8800000000072 +#define FE_JNC 0x48a8800000000073 +#define FE_JZ 0x49a8800000000074 +#define FE_JNZ 0x4aa8800000000075 +#define FE_JBE 0x4ba8800000000076 +#define FE_JA 0x4ca8800000000077 +#define FE_JS 0x4da8800000000078 +#define FE_JNS 0x4ea8800000000079 +#define FE_JP 0x4fa880000000007a +#define FE_JNP 0x50a880000000007b +#define FE_JL 0x51a880000000007c +#define FE_JGE 0x52a880000000007d +#define FE_JLE 0x53a880000000007e +#define FE_JG 0x54a880000000007f +#define FE_ADD8mi 0x20800000000080 +#define FE_LOCK_ADD8mi 0x20800000800080 +#define FE_OR8mi 0x20800000000180 +#define FE_LOCK_OR8mi 0x20800000800180 +#define FE_ADC8mi 0x20800000000280 +#define FE_LOCK_ADC8mi 0x20800000800280 +#define FE_SBB8mi 0x20800000000380 +#define FE_LOCK_SBB8mi 0x20800000800380 +#define FE_AND8mi 0x20800000000480 +#define FE_LOCK_AND8mi 0x20800000800480 +#define FE_SUB8mi 0x20800000000580 +#define FE_LOCK_SUB8mi 0x20800000800580 +#define FE_XOR8mi 0x20800000000680 +#define FE_LOCK_XOR8mi 0x20800000800680 +#define FE_CMP8mi 0x20800000000780 +#define FE_ADD16mi 0x5520800000080083 +#define FE_LOCK_ADD16mi 0x5620800000880083 +#define FE_ADD32mi 0x5720800000000083 +#define FE_LOCK_ADD32mi 0x5820800000800083 +#define FE_ADD64mi 0x5920800000400083 +#define FE_LOCK_ADD64mi 0x5a20800000c00083 +#define FE_OR16mi 0x5b20800000080183 +#define FE_LOCK_OR16mi 0x5c20800000880183 +#define FE_OR32mi 0x5d20800000000183 +#define FE_LOCK_OR32mi 0x5e20800000800183 +#define FE_OR64mi 0x5f20800000400183 +#define FE_LOCK_OR64mi 0x6020800000c00183 +#define FE_ADC16mi 0x6120800000080283 +#define FE_LOCK_ADC16mi 0x6220800000880283 +#define FE_ADC32mi 0x6320800000000283 +#define FE_LOCK_ADC32mi 0x6420800000800283 +#define FE_ADC64mi 0x6520800000400283 +#define FE_LOCK_ADC64mi 0x6620800000c00283 +#define FE_SBB16mi 0x6720800000080383 +#define FE_LOCK_SBB16mi 0x6820800000880383 +#define FE_SBB32mi 0x6920800000000383 +#define FE_LOCK_SBB32mi 0x6a20800000800383 +#define FE_SBB64mi 0x6b20800000400383 +#define FE_LOCK_SBB64mi 0x6c20800000c00383 +#define FE_AND16mi 0x6d20800000080483 +#define FE_LOCK_AND16mi 0x6e20800000880483 +#define FE_AND32mi 0x6f20800000000483 +#define FE_LOCK_AND32mi 0x7020800000800483 +#define FE_AND64mi 0x7120800000400483 +#define FE_LOCK_AND64mi 0x7220800000c00483 +#define FE_SUB16mi 0x7320800000080583 +#define FE_LOCK_SUB16mi 0x7420800000880583 +#define FE_SUB32mi 0x7520800000000583 +#define FE_LOCK_SUB32mi 0x7620800000800583 +#define FE_SUB64mi 0x7720800000400583 +#define FE_LOCK_SUB64mi 0x7820800000c00583 +#define FE_XOR16mi 0x7920800000080683 +#define FE_LOCK_XOR16mi 0x7a20800000880683 +#define FE_XOR32mi 0x7b20800000000683 +#define FE_LOCK_XOR32mi 0x7c20800000800683 +#define FE_XOR64mi 0x7d20800000400683 +#define FE_LOCK_XOR64mi 0x7e20800000c00683 +#define FE_CMP16mi 0x7f20800000080783 +#define FE_CMP32mi 0x8020800000000783 +#define FE_CMP64mi 0x8120800000400783 +#define FE_TEST8mr 0x30400000000084 +#define FE_TEST8rr 0x30600000000084 +#define FE_TEST16mr 0x30000000080085 +#define FE_TEST16rr 0x30000000080085 +#define FE_TEST32mr 0x30000000000085 +#define FE_TEST32rr 0x30000000000085 +#define FE_TEST64mr 0x30000000400085 +#define FE_TEST64rr 0x30000000400085 +#define FE_XCHG8mr 0x30400000000086 +#define FE_XCHG8rr 0x30600000000086 +#define FE_LOCK_XCHG8mr 0x30400000800086 +#define FE_XCHG16mr 0x30000000080087 +#define FE_XCHG16rr 0x8290000000080090 +#define FE_LOCK_XCHG16mr 0x30000000880087 +#define FE_XCHG32mr 0x30000000000087 +#define FE_XCHG32rr 0x8390000000000090 +#define FE_LOCK_XCHG32mr 0x30000000800087 +#define FE_XCHG64mr 0x30000000400087 +#define FE_XCHG64rr 0x8490000000400090 +#define FE_LOCK_XCHG64mr 0x30000000c00087 +#define FE_MOV8mr 0x30400000000088 +#define FE_MOV8rr 0x30600000000088 +#define FE_MOV16mr 0x30000000080089 +#define FE_MOV16rr 0x30000000080089 +#define FE_MOV32mr 0x30000000000089 +#define FE_MOV32rr 0x30000000000089 +#define FE_MOV64mr 0x30000000400089 +#define FE_MOV64rr 0x30000000400089 +#define FE_MOV8rm 0x3820000000008a +#define FE_MOV16rm 0x3800000008008b +#define FE_MOV32rm 0x3800000000008b +#define FE_MOV64rm 0x3800000040008b +#define FE_MOV_S2Gmr 0x3000000000008c +#define FE_MOV_S2Grr 0x3000000000008c +#define FE_LEA16rm 0x3800000008008d +#define FE_LEA32rm 0x3800000000008d +#define FE_LEA64rm 0x3800000040008d +#define FE_MOV_G2Srm 0x3800000000008e +#define FE_MOV_G2Srr 0x3800000000008e +#define FE_POP16m 0x1000000008008f +#define FE_POPm 0x1000000000008f +#define FE_C_EX16 0x8000000080098 +#define FE_C_EX32 0x8000000000098 +#define FE_C_EX64 0x8000000400098 +#define FE_C_SEP16 0x8000000080099 +#define FE_C_SEP32 0x8000000000099 +#define FE_C_SEP64 0x8000000400099 +#define FE_FWAIT 0x800000000009b +#define FE_PUSHF16 0x800000008009c +#define FE_PUSHF 0x800000000009c +#define FE_POPF16 0x800000008009d +#define FE_POPF 0x800000000009d +#define FE_SAHF 0x800000000009e +#define FE_LAHF 0x800000000009f +#define FE_MOV8ra 0xb02000000000a0 +#define FE_MOV16ra 0xb00000000800a1 +#define FE_MOV32ra 0xb00000000000a1 +#define FE_MOV64ra 0xb00000004000a1 +#define FE_MOV8ar 0xb84000000000a2 +#define FE_MOV16ar 0xb80000000800a3 +#define FE_MOV32ar 0xb80000000000a3 +#define FE_MOV64ar 0xb80000004000a3 +#define FE_MOVS8 0x80000000000a4 +#define FE_REP_MOVS8 0x80000002000a4 +#define FE_MOVS16 0x80000000800a5 +#define FE_REP_MOVS16 0x80000002800a5 +#define FE_MOVS32 0x80000000000a5 +#define FE_REP_MOVS32 0x80000002000a5 +#define FE_MOVS64 0x80000004000a5 +#define FE_REP_MOVS64 0x80000006000a5 +#define FE_CMPS8 0x80000000000a6 +#define FE_REPNZ_CMPS8 0x80000001000a6 +#define FE_REPZ_CMPS8 0x80000002000a6 +#define FE_CMPS16 0x80000000800a7 +#define FE_REPNZ_CMPS16 0x80000001800a7 +#define FE_REPZ_CMPS16 0x80000002800a7 +#define FE_CMPS32 0x80000000000a7 +#define FE_REPNZ_CMPS32 0x80000001000a7 +#define FE_REPZ_CMPS32 0x80000002000a7 +#define FE_CMPS64 0x80000004000a7 +#define FE_REPNZ_CMPS64 0x80000005000a7 +#define FE_REPZ_CMPS64 0x80000006000a7 +#define FE_TEST8ri 0x8578a000000000a8 +#define FE_TEST16ri 0x86790000000800a9 +#define FE_TEST32ri 0x877a0000000000a9 +#define FE_TEST64ri 0x887a0000004000a9 +#define FE_STOS8 0x80000000000aa +#define FE_REP_STOS8 0x80000002000aa +#define FE_STOS16 0x80000000800ab +#define FE_REP_STOS16 0x80000002800ab +#define FE_STOS32 0x80000000000ab +#define FE_REP_STOS32 0x80000002000ab +#define FE_STOS64 0x80000004000ab +#define FE_REP_STOS64 0x80000006000ab +#define FE_LODS8 0x80000000000ac +#define FE_REP_LODS8 0x80000002000ac +#define FE_LODS16 0x80000000800ad +#define FE_REP_LODS16 0x80000002800ad +#define FE_LODS32 0x80000000000ad +#define FE_REP_LODS32 0x80000002000ad +#define FE_LODS64 0x80000004000ad +#define FE_REP_LODS64 0x80000006000ad +#define FE_SCAS8 0x80000000000ae +#define FE_REPNZ_SCAS8 0x80000001000ae +#define FE_REPZ_SCAS8 0x80000002000ae +#define FE_SCAS16 0x80000000800af +#define FE_REPNZ_SCAS16 0x80000001800af +#define FE_REPZ_SCAS16 0x80000002800af +#define FE_SCAS32 0x80000000000af +#define FE_REPNZ_SCAS32 0x80000001000af +#define FE_REPZ_SCAS32 0x80000002000af +#define FE_SCAS64 0x80000004000af +#define FE_REPNZ_SCAS64 0x80000005000af +#define FE_REPZ_SCAS64 0x80000006000af +#define FE_MOV8ri 0x8988a000000000b0 +#define FE_MOV16ri 0x8a890000000800b8 +#define FE_MOV32ri 0x8b8a0000000000b8 +#define FE_MOV64ri 0x8c220000004000c7 +#define FE_ROL8mi 0x8d180000000000d0 +#define FE_ROL8ri 0x8e182000000000d0 +#define FE_ROR8mi 0x8f180000000001d0 +#define FE_ROR8ri 0x90182000000001d0 +#define FE_RCL8mi 0x91180000000002d0 +#define FE_RCL8ri 0x92182000000002d0 +#define FE_RCR8mi 0x93180000000003d0 +#define FE_RCR8ri 0x94182000000003d0 +#define FE_SHL8mi 0x95180000000004d0 +#define FE_SHL8ri 0x96182000000004d0 +#define FE_SHR8mi 0x97180000000005d0 +#define FE_SHR8ri 0x98182000000005d0 +#define FE_SAR8mi 0x99180000000007d0 +#define FE_SAR8ri 0x9a182000000007d0 +#define FE_ROL16mi 0x9b180000000800d1 +#define FE_ROL16ri 0x9c180000000800d1 +#define FE_ROL32mi 0x9d180000000000d1 +#define FE_ROL32ri 0x9e180000000000d1 +#define FE_ROL64mi 0x9f180000004000d1 +#define FE_ROL64ri 0xa0180000004000d1 +#define FE_ROR16mi 0xa1180000000801d1 +#define FE_ROR16ri 0xa2180000000801d1 +#define FE_ROR32mi 0xa3180000000001d1 +#define FE_ROR32ri 0xa4180000000001d1 +#define FE_ROR64mi 0xa5180000004001d1 +#define FE_ROR64ri 0xa6180000004001d1 +#define FE_RCL16mi 0xa7180000000802d1 +#define FE_RCL16ri 0xa8180000000802d1 +#define FE_RCL32mi 0xa9180000000002d1 +#define FE_RCL32ri 0xaa180000000002d1 +#define FE_RCL64mi 0xab180000004002d1 +#define FE_RCL64ri 0xac180000004002d1 +#define FE_RCR16mi 0xad180000000803d1 +#define FE_RCR16ri 0xae180000000803d1 +#define FE_RCR32mi 0xaf180000000003d1 +#define FE_RCR32ri 0xb0180000000003d1 +#define FE_RCR64mi 0xb1180000004003d1 +#define FE_RCR64ri 0xb2180000004003d1 +#define FE_SHL16mi 0xb3180000000804d1 +#define FE_SHL16ri 0xb4180000000804d1 +#define FE_SHL32mi 0xb5180000000004d1 +#define FE_SHL32ri 0xb6180000000004d1 +#define FE_SHL64mi 0xb7180000004004d1 +#define FE_SHL64ri 0xb8180000004004d1 +#define FE_SHR16mi 0xb9180000000805d1 +#define FE_SHR16ri 0xba180000000805d1 +#define FE_SHR32mi 0xbb180000000005d1 +#define FE_SHR32ri 0xbc180000000005d1 +#define FE_SHR64mi 0xbd180000004005d1 +#define FE_SHR64ri 0xbe180000004005d1 +#define FE_SAR16mi 0xbf180000000807d1 +#define FE_SAR16ri 0xc0180000000807d1 +#define FE_SAR32mi 0xc1180000000007d1 +#define FE_SAR32ri 0xc2180000000007d1 +#define FE_SAR64mi 0xc3180000004007d1 +#define FE_SAR64ri 0xc4180000004007d1 +#define FE_RETi 0x710000000000c2 +#define FE_RET 0x80000000000c3 +#define FE_MOV8mi 0x208000000000c6 +#define FE_XABORTi 0x7080000000f8c6 +#define FE_MOV16mi 0x210000000800c7 +#define FE_MOV32mi 0x220000000000c7 +#define FE_MOV64mi 0x220000004000c7 +#define FE_XBEGIN 0xaa00000000f8c7 +#define FE_ENTER16i 0x718000000800c8 +#define FE_ENTERi 0x718000000000c8 +#define FE_LEAVE16 0x80000000800c9 +#define FE_LEAVE 0x80000000000c9 +#define FE_RETF16i 0x710000000800ca +#define FE_RETF32i 0x710000000000ca +#define FE_RETF64i 0x710000004000ca +#define FE_RETF16 0x80000000800cb +#define FE_RETF32 0x80000000000cb +#define FE_RETF64 0x80000004000cb +#define FE_INT3 0x80000000000cc +#define FE_INTi 0x708000000000cd +#define FE_IRET16 0x80000000800cf +#define FE_IRET32 0x80000000000cf +#define FE_IRET64 0x80000004000cf +#define FE_ROL8mr 0x284000000000d2 +#define FE_ROL8rr 0x286000000000d2 +#define FE_ROR8mr 0x284000000001d2 +#define FE_ROR8rr 0x286000000001d2 +#define FE_RCL8mr 0x284000000002d2 +#define FE_RCL8rr 0x286000000002d2 +#define FE_RCR8mr 0x284000000003d2 +#define FE_RCR8rr 0x286000000003d2 +#define FE_SHL8mr 0x284000000004d2 +#define FE_SHL8rr 0x286000000004d2 +#define FE_SHR8mr 0x284000000005d2 +#define FE_SHR8rr 0x286000000005d2 +#define FE_SAR8mr 0x284000000007d2 +#define FE_SAR8rr 0x286000000007d2 +#define FE_ROL16mr 0x280000000800d3 +#define FE_ROL16rr 0x280000000800d3 +#define FE_ROL32mr 0x280000000000d3 +#define FE_ROL32rr 0x280000000000d3 +#define FE_ROL64mr 0x280000004000d3 +#define FE_ROL64rr 0x280000004000d3 +#define FE_ROR16mr 0x280000000801d3 +#define FE_ROR16rr 0x280000000801d3 +#define FE_ROR32mr 0x280000000001d3 +#define FE_ROR32rr 0x280000000001d3 +#define FE_ROR64mr 0x280000004001d3 +#define FE_ROR64rr 0x280000004001d3 +#define FE_RCL16mr 0x280000000802d3 +#define FE_RCL16rr 0x280000000802d3 +#define FE_RCL32mr 0x280000000002d3 +#define FE_RCL32rr 0x280000000002d3 +#define FE_RCL64mr 0x280000004002d3 +#define FE_RCL64rr 0x280000004002d3 +#define FE_RCR16mr 0x280000000803d3 +#define FE_RCR16rr 0x280000000803d3 +#define FE_RCR32mr 0x280000000003d3 +#define FE_RCR32rr 0x280000000003d3 +#define FE_RCR64mr 0x280000004003d3 +#define FE_RCR64rr 0x280000004003d3 +#define FE_SHL16mr 0x280000000804d3 +#define FE_SHL16rr 0x280000000804d3 +#define FE_SHL32mr 0x280000000004d3 +#define FE_SHL32rr 0x280000000004d3 +#define FE_SHL64mr 0x280000004004d3 +#define FE_SHL64rr 0x280000004004d3 +#define FE_SHR16mr 0x280000000805d3 +#define FE_SHR16rr 0x280000000805d3 +#define FE_SHR32mr 0x280000000005d3 +#define FE_SHR32rr 0x280000000005d3 +#define FE_SHR64mr 0x280000004005d3 +#define FE_SHR64rr 0x280000004005d3 +#define FE_SAR16mr 0x280000000807d3 +#define FE_SAR16rr 0x280000000807d3 +#define FE_SAR32mr 0x280000000007d3 +#define FE_SAR32rr 0x280000000007d3 +#define FE_SAR64mr 0x280000004007d3 +#define FE_SAR64rr 0x280000004007d3 +#define FE_XLATB 0x80000000000d7 +#define FE_LOOPNZ 0xa88000000000e0 +#define FE_LOOPZ 0xa88000000000e1 +#define FE_LOOP 0xa88000000000e2 +#define FE_JCXZ 0xa88000000000e3 +#define FE_IN8ri 0x78a000000000e4 +#define FE_IN16ri 0x788000000800e5 +#define FE_IN32ri 0x788000000000e5 +#define FE_IN64ri 0x788000004000e5 +#define FE_OUT8ri 0x78a000000000e6 +#define FE_OUT16ri 0x788000000800e7 +#define FE_OUT32ri 0x788000000000e7 +#define FE_OUT64ri 0x788000004000e7 +#define FE_CALL 0xaa0000000000e8 +#define FE_JMP 0xc5a88000000000eb +#define FE_IN8 0x80000000000ec +#define FE_IN16 0x80000000800ed +#define FE_IN32 0x80000000000ed +#define FE_IN64 0x80000004000ed +#define FE_OUT8 0x80000000000ee +#define FE_OUT16 0x80000000800ef +#define FE_OUT32 0x80000000000ef +#define FE_OUT64 0x80000004000ef +#define FE_INT1 0x80000000000f1 +#define FE_HLT 0x80000000000f4 +#define FE_CMC 0x80000000000f5 +#define FE_TEST8mi 0x208000000000f6 +#define FE_NOT8m 0x100000000002f6 +#define FE_NOT8r 0x102000000002f6 +#define FE_LOCK_NOT8m 0x100000008002f6 +#define FE_NEG8m 0x100000000003f6 +#define FE_NEG8r 0x102000000003f6 +#define FE_LOCK_NEG8m 0x100000008003f6 +#define FE_MUL8m 0x100000000004f6 +#define FE_MUL8r 0x102000000004f6 +#define FE_IMUL8m 0x100000000005f6 +#define FE_IMUL8r 0x102000000005f6 +#define FE_DIV8m 0x100000000006f6 +#define FE_DIV8r 0x102000000006f6 +#define FE_IDIV8m 0x100000000007f6 +#define FE_IDIV8r 0x102000000007f6 +#define FE_TEST16mi 0x210000000800f7 +#define FE_TEST32mi 0x220000000000f7 +#define FE_TEST64mi 0x220000004000f7 +#define FE_NOT16m 0x100000000802f7 +#define FE_NOT16r 0x100000000802f7 +#define FE_LOCK_NOT16m 0x100000008802f7 +#define FE_NOT32m 0x100000000002f7 +#define FE_NOT32r 0x100000000002f7 +#define FE_LOCK_NOT32m 0x100000008002f7 +#define FE_NOT64m 0x100000004002f7 +#define FE_NOT64r 0x100000004002f7 +#define FE_LOCK_NOT64m 0x10000000c002f7 +#define FE_NEG16m 0x100000000803f7 +#define FE_NEG16r 0x100000000803f7 +#define FE_LOCK_NEG16m 0x100000008803f7 +#define FE_NEG32m 0x100000000003f7 +#define FE_NEG32r 0x100000000003f7 +#define FE_LOCK_NEG32m 0x100000008003f7 +#define FE_NEG64m 0x100000004003f7 +#define FE_NEG64r 0x100000004003f7 +#define FE_LOCK_NEG64m 0x10000000c003f7 +#define FE_MUL16m 0x100000000804f7 +#define FE_MUL16r 0x100000000804f7 +#define FE_MUL32m 0x100000000004f7 +#define FE_MUL32r 0x100000000004f7 +#define FE_MUL64m 0x100000004004f7 +#define FE_MUL64r 0x100000004004f7 +#define FE_IMUL16m 0x100000000805f7 +#define FE_IMUL16r 0x100000000805f7 +#define FE_IMUL32m 0x100000000005f7 +#define FE_IMUL32r 0x100000000005f7 +#define FE_IMUL64m 0x100000004005f7 +#define FE_IMUL64r 0x100000004005f7 +#define FE_DIV16m 0x100000000806f7 +#define FE_DIV16r 0x100000000806f7 +#define FE_DIV32m 0x100000000006f7 +#define FE_DIV32r 0x100000000006f7 +#define FE_DIV64m 0x100000004006f7 +#define FE_DIV64r 0x100000004006f7 +#define FE_IDIV16m 0x100000000807f7 +#define FE_IDIV16r 0x100000000807f7 +#define FE_IDIV32m 0x100000000007f7 +#define FE_IDIV32r 0x100000000007f7 +#define FE_IDIV64m 0x100000004007f7 +#define FE_IDIV64r 0x100000004007f7 +#define FE_CLC 0x80000000000f8 +#define FE_STC 0x80000000000f9 +#define FE_CLI 0x80000000000fa +#define FE_STI 0x80000000000fb +#define FE_CLD 0x80000000000fc +#define FE_STD 0x80000000000fd +#define FE_INC8m 0x100000000000fe +#define FE_INC8r 0x102000000000fe +#define FE_LOCK_INC8m 0x100000008000fe +#define FE_DEC8m 0x100000000001fe +#define FE_DEC8r 0x102000000001fe +#define FE_LOCK_DEC8m 0x100000008001fe +#define FE_INC16m 0x100000000800ff +#define FE_INC16r 0x100000000800ff +#define FE_LOCK_INC16m 0x100000008800ff +#define FE_INC32m 0x100000000000ff +#define FE_INC32r 0x100000000000ff +#define FE_LOCK_INC32m 0x100000008000ff +#define FE_INC64m 0x100000004000ff +#define FE_INC64r 0x100000004000ff +#define FE_LOCK_INC64m 0x10000000c000ff +#define FE_DEC16m 0x100000000801ff +#define FE_DEC16r 0x100000000801ff +#define FE_LOCK_DEC16m 0x100000008801ff +#define FE_DEC32m 0x100000000001ff +#define FE_DEC32r 0x100000000001ff +#define FE_LOCK_DEC32m 0x100000008001ff +#define FE_DEC64m 0x100000004001ff +#define FE_DEC64r 0x100000004001ff +#define FE_LOCK_DEC64m 0x10000000c001ff +#define FE_CALLm 0x100000000002ff +#define FE_CALLr 0x100000000002ff +#define FE_CALLF16m 0x100000000803ff +#define FE_CALLF32m 0x100000000003ff +#define FE_CALLF64m 0x100000004003ff +#define FE_JMPm 0x100000000004ff +#define FE_JMPr 0x100000000004ff +#define FE_JMPF16m 0x100000000805ff +#define FE_JMPF32m 0x100000000005ff +#define FE_JMPF64m 0x100000004005ff +#define FE_PUSH16m 0x100000000806ff +#define FE_PUSHm 0x100000000006ff +#define FE_SLDTm 0x10000000010000 +#define FE_SLDTr 0x10000000010000 +#define FE_STRm 0x10000000010100 +#define FE_STRr 0x10000000010100 +#define FE_LLDTm 0x10000000010200 +#define FE_LLDTr 0x10000000010200 +#define FE_LTRm 0x10000000010300 +#define FE_LTRr 0x10000000010300 +#define FE_VERRm 0x10000000010400 +#define FE_VERRr 0x10000000010400 +#define FE_VERWm 0x10000000010500 +#define FE_VERWr 0x10000000010500 +#define FE_SGDTm 0x10000000010001 +#define FE_SIDTm 0x10000000010101 +#define FE_LGDTm 0x10000000010201 +#define FE_LIDTm 0x10000000010301 +#define FE_SMSWm 0x10000000010401 +#define FE_SMSW16r 0x10000000090401 +#define FE_SMSW32r 0x10000000010401 +#define FE_SMSW64r 0x10000000410401 +#define FE_LMSWm 0x10000000010601 +#define FE_LMSWr 0x10000000010601 +#define FE_INVLPG8m 0x10000000010701 +#define FE_ENCLV 0x800000001c001 +#define FE_MONITOR 0x800000001c801 +#define FE_MWAIT 0x800000001c901 +#define FE_CLAC 0x800000001ca01 +#define FE_STAC 0x800000001cb01 +#define FE_ENCLS 0x800000001cf01 +#define FE_XGETBV 0x800000001d001 +#define FE_XSETBV 0x800000001d101 +#define FE_XEND 0x800000001d501 +#define FE_XTEST 0x800000001d601 +#define FE_ENCLU 0x800000001d701 +#define FE_SWAPGS 0x800000001f801 +#define FE_RDTSCP 0x800000001f901 +#define FE_LAR16rm 0x38000000090002 +#define FE_LAR16rr 0x38000000090002 +#define FE_LAR32rm 0x38000000010002 +#define FE_LAR32rr 0x38000000010002 +#define FE_LAR64rm 0x38000000410002 +#define FE_LAR64rr 0x38000000410002 +#define FE_LSL16rm 0x38000000090003 +#define FE_LSL16rr 0x38000000090003 +#define FE_LSL32rm 0x38000000010003 +#define FE_LSL32rr 0x38000000010003 +#define FE_LSL64rm 0x38000000410003 +#define FE_LSL64rr 0x38000000410003 +#define FE_SYSCALL 0x8000000010005 +#define FE_CLTS 0x8000000010006 +#define FE_SYSRET 0x8000000010007 +#define FE_INVD 0x8000000010008 +#define FE_WBINVD 0x8000000010009 +#define FE_UD2 0x800000001000b +#define FE_PREFETCHm 0x1000000001000d +#define FE_PREFETCHWm 0x1000000001010d +#define FE_PREFETCHWT1m 0x1000000001020d +#define FE_FEMMS 0x800000001000e +#define FE_3DNOWrmi 0x5080000001000f +#define FE_3DNOWrri 0x5080000001000f +#define FE_PREFETCHNTAm 0x10000000010018 +#define FE_PREFETCHT0m 0x10000000010118 +#define FE_PREFETCHT1m 0x10000000010218 +#define FE_PREFETCHT2m 0x10000000010318 +#define FE_PREFETCHIT1m 0x10000000010618 +#define FE_PREFETCHIT0m 0x10000000010718 +#define FE_NOP16m 0x1000000009001f +#define FE_NOP16r 0x1000000009001f +#define FE_NOP32m 0x1000000001001f +#define FE_NOP32r 0x1000000001001f +#define FE_NOP64m 0x1000000041001f +#define FE_NOP64r 0x1000000041001f +#define FE_MOV_CR2Gmr 0x30000000010020 +#define FE_MOV_CR2Grr 0x30000000010020 +#define FE_MOV_DR2Gmr 0x30000000010021 +#define FE_MOV_DR2Grr 0x30000000010021 +#define FE_MOV_G2CRrm 0x38000000010022 +#define FE_MOV_G2CRrr 0x38000000010022 +#define FE_MOV_G2DRrm 0x38000000010023 +#define FE_MOV_G2DRrr 0x38000000010023 +#define FE_WRMSR 0x8000000010030 +#define FE_RDTSC 0x8000000010031 +#define FE_RDMSR 0x8000000010032 +#define FE_RDPMC 0x8000000010033 +#define FE_SYSENTER 0x8000000010034 +#define FE_SYSEXIT 0x8000000010035 +#define FE_GETSEC 0x8000000010037 +#define FE_CMOVO16rm 0x38000000090040 +#define FE_CMOVO16rr 0x38000000090040 +#define FE_CMOVO32rm 0x38000000010040 +#define FE_CMOVO32rr 0x38000000010040 +#define FE_CMOVO64rm 0x38000000410040 +#define FE_CMOVO64rr 0x38000000410040 +#define FE_CMOVNO16rm 0x38000000090041 +#define FE_CMOVNO16rr 0x38000000090041 +#define FE_CMOVNO32rm 0x38000000010041 +#define FE_CMOVNO32rr 0x38000000010041 +#define FE_CMOVNO64rm 0x38000000410041 +#define FE_CMOVNO64rr 0x38000000410041 +#define FE_CMOVC16rm 0x38000000090042 +#define FE_CMOVC16rr 0x38000000090042 +#define FE_CMOVC32rm 0x38000000010042 +#define FE_CMOVC32rr 0x38000000010042 +#define FE_CMOVC64rm 0x38000000410042 +#define FE_CMOVC64rr 0x38000000410042 +#define FE_CMOVNC16rm 0x38000000090043 +#define FE_CMOVNC16rr 0x38000000090043 +#define FE_CMOVNC32rm 0x38000000010043 +#define FE_CMOVNC32rr 0x38000000010043 +#define FE_CMOVNC64rm 0x38000000410043 +#define FE_CMOVNC64rr 0x38000000410043 +#define FE_CMOVZ16rm 0x38000000090044 +#define FE_CMOVZ16rr 0x38000000090044 +#define FE_CMOVZ32rm 0x38000000010044 +#define FE_CMOVZ32rr 0x38000000010044 +#define FE_CMOVZ64rm 0x38000000410044 +#define FE_CMOVZ64rr 0x38000000410044 +#define FE_CMOVNZ16rm 0x38000000090045 +#define FE_CMOVNZ16rr 0x38000000090045 +#define FE_CMOVNZ32rm 0x38000000010045 +#define FE_CMOVNZ32rr 0x38000000010045 +#define FE_CMOVNZ64rm 0x38000000410045 +#define FE_CMOVNZ64rr 0x38000000410045 +#define FE_CMOVBE16rm 0x38000000090046 +#define FE_CMOVBE16rr 0x38000000090046 +#define FE_CMOVBE32rm 0x38000000010046 +#define FE_CMOVBE32rr 0x38000000010046 +#define FE_CMOVBE64rm 0x38000000410046 +#define FE_CMOVBE64rr 0x38000000410046 +#define FE_CMOVA16rm 0x38000000090047 +#define FE_CMOVA16rr 0x38000000090047 +#define FE_CMOVA32rm 0x38000000010047 +#define FE_CMOVA32rr 0x38000000010047 +#define FE_CMOVA64rm 0x38000000410047 +#define FE_CMOVA64rr 0x38000000410047 +#define FE_CMOVS16rm 0x38000000090048 +#define FE_CMOVS16rr 0x38000000090048 +#define FE_CMOVS32rm 0x38000000010048 +#define FE_CMOVS32rr 0x38000000010048 +#define FE_CMOVS64rm 0x38000000410048 +#define FE_CMOVS64rr 0x38000000410048 +#define FE_CMOVNS16rm 0x38000000090049 +#define FE_CMOVNS16rr 0x38000000090049 +#define FE_CMOVNS32rm 0x38000000010049 +#define FE_CMOVNS32rr 0x38000000010049 +#define FE_CMOVNS64rm 0x38000000410049 +#define FE_CMOVNS64rr 0x38000000410049 +#define FE_CMOVP16rm 0x3800000009004a +#define FE_CMOVP16rr 0x3800000009004a +#define FE_CMOVP32rm 0x3800000001004a +#define FE_CMOVP32rr 0x3800000001004a +#define FE_CMOVP64rm 0x3800000041004a +#define FE_CMOVP64rr 0x3800000041004a +#define FE_CMOVNP16rm 0x3800000009004b +#define FE_CMOVNP16rr 0x3800000009004b +#define FE_CMOVNP32rm 0x3800000001004b +#define FE_CMOVNP32rr 0x3800000001004b +#define FE_CMOVNP64rm 0x3800000041004b +#define FE_CMOVNP64rr 0x3800000041004b +#define FE_CMOVL16rm 0x3800000009004c +#define FE_CMOVL16rr 0x3800000009004c +#define FE_CMOVL32rm 0x3800000001004c +#define FE_CMOVL32rr 0x3800000001004c +#define FE_CMOVL64rm 0x3800000041004c +#define FE_CMOVL64rr 0x3800000041004c +#define FE_CMOVGE16rm 0x3800000009004d +#define FE_CMOVGE16rr 0x3800000009004d +#define FE_CMOVGE32rm 0x3800000001004d +#define FE_CMOVGE32rr 0x3800000001004d +#define FE_CMOVGE64rm 0x3800000041004d +#define FE_CMOVGE64rr 0x3800000041004d +#define FE_CMOVLE16rm 0x3800000009004e +#define FE_CMOVLE16rr 0x3800000009004e +#define FE_CMOVLE32rm 0x3800000001004e +#define FE_CMOVLE32rr 0x3800000001004e +#define FE_CMOVLE64rm 0x3800000041004e +#define FE_CMOVLE64rr 0x3800000041004e +#define FE_CMOVG16rm 0x3800000009004f +#define FE_CMOVG16rr 0x3800000009004f +#define FE_CMOVG32rm 0x3800000001004f +#define FE_CMOVG32rr 0x3800000001004f +#define FE_CMOVG64rm 0x3800000041004f +#define FE_CMOVG64rr 0x3800000041004f +#define FE_SETO8m 0x10000000010090 +#define FE_SETO8r 0x10200000010090 +#define FE_SETNO8m 0x10000000010091 +#define FE_SETNO8r 0x10200000010091 +#define FE_SETC8m 0x10000000010092 +#define FE_SETC8r 0x10200000010092 +#define FE_SETNC8m 0x10000000010093 +#define FE_SETNC8r 0x10200000010093 +#define FE_SETZ8m 0x10000000010094 +#define FE_SETZ8r 0x10200000010094 +#define FE_SETNZ8m 0x10000000010095 +#define FE_SETNZ8r 0x10200000010095 +#define FE_SETBE8m 0x10000000010096 +#define FE_SETBE8r 0x10200000010096 +#define FE_SETA8m 0x10000000010097 +#define FE_SETA8r 0x10200000010097 +#define FE_SETS8m 0x10000000010098 +#define FE_SETS8r 0x10200000010098 +#define FE_SETNS8m 0x10000000010099 +#define FE_SETNS8r 0x10200000010099 +#define FE_SETP8m 0x1000000001009a +#define FE_SETP8r 0x1020000001009a +#define FE_SETNP8m 0x1000000001009b +#define FE_SETNP8r 0x1020000001009b +#define FE_SETL8m 0x1000000001009c +#define FE_SETL8r 0x1020000001009c +#define FE_SETGE8m 0x1000000001009d +#define FE_SETGE8r 0x1020000001009d +#define FE_SETLE8m 0x1000000001009e +#define FE_SETLE8r 0x1020000001009e +#define FE_SETG8m 0x1000000001009f +#define FE_SETG8r 0x1020000001009f +#define FE_PUSH_SEG16r 0xc6980000000900a0 +#define FE_PUSH_SEGr 0xc7980000000100a0 +#define FE_POP_SEG16r 0xc8980000000900a1 +#define FE_POP_SEGr 0xc9980000000100a1 +#define FE_CPUID 0x80000000100a2 +#define FE_BT16mr 0x300000000900a3 +#define FE_BT16rr 0x300000000900a3 +#define FE_BT32mr 0x300000000100a3 +#define FE_BT32rr 0x300000000100a3 +#define FE_BT64mr 0x300000004100a3 +#define FE_BT64rr 0x300000004100a3 +#define FE_SHLD16rri 0x488000000900a4 +#define FE_SHLD16mri 0x488000000900a4 +#define FE_SHLD32rri 0x488000000100a4 +#define FE_SHLD32mri 0x488000000100a4 +#define FE_SHLD64rri 0x488000004100a4 +#define FE_SHLD64mri 0x488000004100a4 +#define FE_SHLD16mrr 0x580000000900a5 +#define FE_SHLD16rrr 0x580000000900a5 +#define FE_SHLD32mrr 0x580000000100a5 +#define FE_SHLD32rrr 0x580000000100a5 +#define FE_SHLD64mrr 0x580000004100a5 +#define FE_SHLD64rrr 0x580000004100a5 +#define FE_RSM 0x80000000100aa +#define FE_BTS16mr 0x300000000900ab +#define FE_BTS16rr 0x300000000900ab +#define FE_LOCK_BTS16mr 0x300000008900ab +#define FE_BTS32mr 0x300000000100ab +#define FE_BTS32rr 0x300000000100ab +#define FE_LOCK_BTS32mr 0x300000008100ab +#define FE_BTS64mr 0x300000004100ab +#define FE_BTS64rr 0x300000004100ab +#define FE_LOCK_BTS64mr 0x30000000c100ab +#define FE_SHRD16rri 0x488000000900ac +#define FE_SHRD16mri 0x488000000900ac +#define FE_SHRD32rri 0x488000000100ac +#define FE_SHRD32mri 0x488000000100ac +#define FE_SHRD64rri 0x488000004100ac +#define FE_SHRD64mri 0x488000004100ac +#define FE_SHRD16mrr 0x580000000900ad +#define FE_SHRD16rrr 0x580000000900ad +#define FE_SHRD32mrr 0x580000000100ad +#define FE_SHRD32rrr 0x580000000100ad +#define FE_SHRD64mrr 0x580000004100ad +#define FE_SHRD64rrr 0x580000004100ad +#define FE_IMUL16rm 0x380000000900af +#define FE_IMUL16rr 0x380000000900af +#define FE_IMUL32rm 0x380000000100af +#define FE_IMUL32rr 0x380000000100af +#define FE_IMUL64rm 0x380000004100af +#define FE_IMUL64rr 0x380000004100af +#define FE_CMPXCHG8mr 0x304000000100b0 +#define FE_CMPXCHG8rr 0x306000000100b0 +#define FE_LOCK_CMPXCHG8mr 0x304000008100b0 +#define FE_CMPXCHG16mr 0x300000000900b1 +#define FE_CMPXCHG16rr 0x300000000900b1 +#define FE_LOCK_CMPXCHG16mr 0x300000008900b1 +#define FE_CMPXCHG32mr 0x300000000100b1 +#define FE_CMPXCHG32rr 0x300000000100b1 +#define FE_LOCK_CMPXCHG32mr 0x300000008100b1 +#define FE_CMPXCHG64mr 0x300000004100b1 +#define FE_CMPXCHG64rr 0x300000004100b1 +#define FE_LOCK_CMPXCHG64mr 0x30000000c100b1 +#define FE_LSS16rm 0x380000000900b2 +#define FE_LSS32rm 0x380000000100b2 +#define FE_LSS64rm 0x380000004100b2 +#define FE_BTR16mr 0x300000000900b3 +#define FE_BTR16rr 0x300000000900b3 +#define FE_LOCK_BTR16mr 0x300000008900b3 +#define FE_BTR32mr 0x300000000100b3 +#define FE_BTR32rr 0x300000000100b3 +#define FE_LOCK_BTR32mr 0x300000008100b3 +#define FE_BTR64mr 0x300000004100b3 +#define FE_BTR64rr 0x300000004100b3 +#define FE_LOCK_BTR64mr 0x30000000c100b3 +#define FE_LFS16rm 0x380000000900b4 +#define FE_LFS32rm 0x380000000100b4 +#define FE_LFS64rm 0x380000004100b4 +#define FE_LGS16rm 0x380000000900b5 +#define FE_LGS32rm 0x380000000100b5 +#define FE_LGS64rm 0x380000004100b5 +#define FE_MOVZXr16m8 0x380000000900b6 +#define FE_MOVZXr16r8 0x384000000900b6 +#define FE_MOVZXr32m8 0x380000000100b6 +#define FE_MOVZXr32r8 0x384000000100b6 +#define FE_MOVZXr64m8 0x380000004100b6 +#define FE_MOVZXr64r8 0x384000004100b6 +#define FE_MOVZXr16m16 0x380000000900b7 +#define FE_MOVZXr16r16 0x380000000900b7 +#define FE_MOVZXr32m16 0x380000000100b7 +#define FE_MOVZXr32r16 0x380000000100b7 +#define FE_MOVZXr64m16 0x380000004100b7 +#define FE_MOVZXr64r16 0x380000004100b7 +#define FE_POPCNT16rm 0x380000002900b8 +#define FE_POPCNT16rr 0x380000002900b8 +#define FE_POPCNT32rm 0x380000002100b8 +#define FE_POPCNT32rr 0x380000002100b8 +#define FE_POPCNT64rm 0x380000006100b8 +#define FE_POPCNT64rr 0x380000006100b8 +#define FE_UD1_16rm 0x380000000900b9 +#define FE_UD1_16rr 0x380000000900b9 +#define FE_UD1_32rm 0x380000000100b9 +#define FE_UD1_32rr 0x380000000100b9 +#define FE_UD1_64rm 0x380000004100b9 +#define FE_UD1_64rr 0x380000004100b9 +#define FE_BT16mi 0x208000000904ba +#define FE_BT16ri 0x208000000904ba +#define FE_BT32mi 0x208000000104ba +#define FE_BT32ri 0x208000000104ba +#define FE_BT64mi 0x208000004104ba +#define FE_BT64ri 0x208000004104ba +#define FE_BTS16mi 0x208000000905ba +#define FE_BTS16ri 0x208000000905ba +#define FE_LOCK_BTS16mi 0x208000008905ba +#define FE_BTS32mi 0x208000000105ba +#define FE_BTS32ri 0x208000000105ba +#define FE_LOCK_BTS32mi 0x208000008105ba +#define FE_BTS64mi 0x208000004105ba +#define FE_BTS64ri 0x208000004105ba +#define FE_LOCK_BTS64mi 0x20800000c105ba +#define FE_BTR16mi 0x208000000906ba +#define FE_BTR16ri 0x208000000906ba +#define FE_LOCK_BTR16mi 0x208000008906ba +#define FE_BTR32mi 0x208000000106ba +#define FE_BTR32ri 0x208000000106ba +#define FE_LOCK_BTR32mi 0x208000008106ba +#define FE_BTR64mi 0x208000004106ba +#define FE_BTR64ri 0x208000004106ba +#define FE_LOCK_BTR64mi 0x20800000c106ba +#define FE_BTC16mi 0x208000000907ba +#define FE_BTC16ri 0x208000000907ba +#define FE_LOCK_BTC16mi 0x208000008907ba +#define FE_BTC32mi 0x208000000107ba +#define FE_BTC32ri 0x208000000107ba +#define FE_LOCK_BTC32mi 0x208000008107ba +#define FE_BTC64mi 0x208000004107ba +#define FE_BTC64ri 0x208000004107ba +#define FE_LOCK_BTC64mi 0x20800000c107ba +#define FE_BTC16mr 0x300000000900bb +#define FE_BTC16rr 0x300000000900bb +#define FE_LOCK_BTC16mr 0x300000008900bb +#define FE_BTC32mr 0x300000000100bb +#define FE_BTC32rr 0x300000000100bb +#define FE_LOCK_BTC32mr 0x300000008100bb +#define FE_BTC64mr 0x300000004100bb +#define FE_BTC64rr 0x300000004100bb +#define FE_LOCK_BTC64mr 0x30000000c100bb +#define FE_BSF16rm 0x380000000900bc +#define FE_BSF16rr 0x380000000900bc +#define FE_BSF32rm 0x380000000100bc +#define FE_BSF32rr 0x380000000100bc +#define FE_BSF64rm 0x380000004100bc +#define FE_BSF64rr 0x380000004100bc +#define FE_TZCNT16rm 0x380000002900bc +#define FE_TZCNT16rr 0x380000002900bc +#define FE_TZCNT32rm 0x380000002100bc +#define FE_TZCNT32rr 0x380000002100bc +#define FE_TZCNT64rm 0x380000006100bc +#define FE_TZCNT64rr 0x380000006100bc +#define FE_BSR16rm 0x380000000900bd +#define FE_BSR16rr 0x380000000900bd +#define FE_BSR32rm 0x380000000100bd +#define FE_BSR32rr 0x380000000100bd +#define FE_BSR64rm 0x380000004100bd +#define FE_BSR64rr 0x380000004100bd +#define FE_LZCNT16rm 0x380000002900bd +#define FE_LZCNT16rr 0x380000002900bd +#define FE_LZCNT32rm 0x380000002100bd +#define FE_LZCNT32rr 0x380000002100bd +#define FE_LZCNT64rm 0x380000006100bd +#define FE_LZCNT64rr 0x380000006100bd +#define FE_MOVSXr16m8 0x380000000900be +#define FE_MOVSXr16r8 0x384000000900be +#define FE_MOVSXr32m8 0x380000000100be +#define FE_MOVSXr32r8 0x384000000100be +#define FE_MOVSXr64m8 0x380000004100be +#define FE_MOVSXr64r8 0x384000004100be +#define FE_MOVSXr16m16 0x380000000900bf +#define FE_MOVSXr16r16 0x380000000900bf +#define FE_MOVSXr32m16 0x380000000100bf +#define FE_MOVSXr32r16 0x380000000100bf +#define FE_MOVSXr64m16 0x380000004100bf +#define FE_MOVSXr64r16 0x380000004100bf +#define FE_XADD8mr 0x304000000100c0 +#define FE_XADD8rr 0x306000000100c0 +#define FE_LOCK_XADD8mr 0x304000008100c0 +#define FE_XADD16mr 0x300000000900c1 +#define FE_XADD16rr 0x300000000900c1 +#define FE_LOCK_XADD16mr 0x300000008900c1 +#define FE_XADD32mr 0x300000000100c1 +#define FE_XADD32rr 0x300000000100c1 +#define FE_LOCK_XADD32mr 0x300000008100c1 +#define FE_XADD64mr 0x300000004100c1 +#define FE_XADD64rr 0x300000004100c1 +#define FE_LOCK_XADD64mr 0x30000000c100c1 +#define FE_MOVNTI32mr 0x300000000100c3 +#define FE_MOVNTI64mr 0x300000004100c3 +#define FE_CMPXCHGD32m 0x100000000101c7 +#define FE_LOCK_CMPXCHGD32m 0x100000008101c7 +#define FE_CMPXCHGD64m 0x100000004101c7 +#define FE_LOCK_CMPXCHGD64m 0x10000000c101c7 +#define FE_BSWAP16r 0x800000000900c8 +#define FE_BSWAP32r 0x800000000100c8 +#define FE_BSWAP64r 0x800000004100c8 +#define FE_UD0_16rm 0x380000000900ff +#define FE_UD0_16rr 0x380000000900ff +#define FE_UD0_32rm 0x380000000100ff +#define FE_UD0_32rr 0x380000000100ff +#define FE_UD0_64rm 0x380000004100ff +#define FE_UD0_64rr 0x380000004100ff +#define FE_MOVBE16rm 0x380000000a00f0 +#define FE_MOVBE32rm 0x380000000200f0 +#define FE_MOVBE64rm 0x380000004200f0 +#define FE_CRC32_8rm 0x380000001200f0 +#define FE_CRC32_8rr 0x384000001200f0 +#define FE_MOVBE16mr 0x300000000a00f1 +#define FE_MOVBE32mr 0x300000000200f1 +#define FE_MOVBE64mr 0x300000004200f1 +#define FE_CRC32_16rm 0x380000001a00f1 +#define FE_CRC32_16rr 0x380000001a00f1 +#define FE_CRC32_32rm 0x380000001200f1 +#define FE_CRC32_32rr 0x380000001200f1 +#define FE_CRC32_64rm 0x380000005200f1 +#define FE_CRC32_64rr 0x380000005200f1 +#define FE_MMX_CVTPI2PSrm 0x3800000001002a +#define FE_MMX_CVTPI2PSrr 0x3800000001002a +#define FE_MMX_CVTPI2PDrm 0x3800000009002a +#define FE_MMX_CVTPI2PDrr 0x3800000009002a +#define FE_MMX_CVTTPS2PIrm 0x3800000001002c +#define FE_MMX_CVTTPS2PIrr 0x3800000001002c +#define FE_MMX_CVTTPD2PIrm 0x3800000009002c +#define FE_MMX_CVTTPD2PIrr 0x3800000009002c +#define FE_MMX_CVTPS2PIrm 0x3800000001002d +#define FE_MMX_CVTPS2PIrr 0x3800000001002d +#define FE_MMX_CVTPD2PIrm 0x3800000009002d +#define FE_MMX_CVTPD2PIrr 0x3800000009002d +#define FE_MMX_PUNPCKLBWrm 0x38000000010060 +#define FE_MMX_PUNPCKLBWrr 0x38000000010060 +#define FE_MMX_PUNPCKLWDrm 0x38000000010061 +#define FE_MMX_PUNPCKLWDrr 0x38000000010061 +#define FE_MMX_PUNPCKLDQrm 0x38000000010062 +#define FE_MMX_PUNPCKLDQrr 0x38000000010062 +#define FE_MMX_PACKSSWBrm 0x38000000010063 +#define FE_MMX_PACKSSWBrr 0x38000000010063 +#define FE_MMX_PCMPGTBrm 0x38000000010064 +#define FE_MMX_PCMPGTBrr 0x38000000010064 +#define FE_MMX_PCMPGTWrm 0x38000000010065 +#define FE_MMX_PCMPGTWrr 0x38000000010065 +#define FE_MMX_PCMPGTDrm 0x38000000010066 +#define FE_MMX_PCMPGTDrr 0x38000000010066 +#define FE_MMX_PACKUSWBrm 0x38000000010067 +#define FE_MMX_PACKUSWBrr 0x38000000010067 +#define FE_MMX_PUNPCKHBWrm 0x38000000010068 +#define FE_MMX_PUNPCKHBWrr 0x38000000010068 +#define FE_MMX_PUNPCKHWDrm 0x38000000010069 +#define FE_MMX_PUNPCKHWDrr 0x38000000010069 +#define FE_MMX_PUNPCKHDQrm 0x3800000001006a +#define FE_MMX_PUNPCKHDQrr 0x3800000001006a +#define FE_MMX_PACKSSDWrm 0x3800000001006b +#define FE_MMX_PACKSSDWrr 0x3800000001006b +#define FE_MMX_MOVD_G2Mrm 0x3800000001006e +#define FE_MMX_MOVD_G2Mrr 0x3800000001006e +#define FE_MMX_MOVQ_G2Mrm 0x3800000041006e +#define FE_MMX_MOVQ_G2Mrr 0x3800000041006e +#define FE_MMX_MOVQrm 0x3800000001006f +#define FE_MMX_MOVQrr 0x3800000001006f +#define FE_MMX_PSHUFWrmi 0x50800000010070 +#define FE_MMX_PSHUFWrri 0x50800000010070 +#define FE_MMX_PSRLWri 0x20800000010271 +#define FE_MMX_PSRAWri 0x20800000010471 +#define FE_MMX_PSLLWri 0x20800000010671 +#define FE_MMX_PSRLDri 0x20800000010272 +#define FE_MMX_PSRADri 0x20800000010472 +#define FE_MMX_PSLLDri 0x20800000010672 +#define FE_MMX_PSRLQri 0x20800000010273 +#define FE_MMX_PSLLQri 0x20800000010673 +#define FE_MMX_PCMPEQBrm 0x38000000010074 +#define FE_MMX_PCMPEQBrr 0x38000000010074 +#define FE_MMX_PCMPEQWrm 0x38000000010075 +#define FE_MMX_PCMPEQWrr 0x38000000010075 +#define FE_MMX_PCMPEQDrm 0x38000000010076 +#define FE_MMX_PCMPEQDrr 0x38000000010076 +#define FE_MMX_EMMS 0x8000000010077 +#define FE_MMX_MOVD_M2Gmr 0x3000000001007e +#define FE_MMX_MOVD_M2Grr 0x3000000001007e +#define FE_MMX_MOVQ_M2Gmr 0x3000000041007e +#define FE_MMX_MOVQ_M2Grr 0x3000000041007e +#define FE_MMX_MOVQmr 0x3000000001007f +#define FE_MMX_PINSRWrmi 0x508000000100c4 +#define FE_MMX_PINSRWrri 0x508000000100c4 +#define FE_MMX_PEXTRWrri 0x508000000100c5 +#define FE_MMX_PSRLWrm 0x380000000100d1 +#define FE_MMX_PSRLWrr 0x380000000100d1 +#define FE_MMX_PSRLDrm 0x380000000100d2 +#define FE_MMX_PSRLDrr 0x380000000100d2 +#define FE_MMX_PSRLQrm 0x380000000100d3 +#define FE_MMX_PSRLQrr 0x380000000100d3 +#define FE_MMX_PADDQrm 0x380000000100d4 +#define FE_MMX_PADDQrr 0x380000000100d4 +#define FE_MMX_PMULLWrm 0x380000000100d5 +#define FE_MMX_PMULLWrr 0x380000000100d5 +#define FE_MMX_MOVDQ2Qrr 0x380000001100d6 +#define FE_MMX_MOVQ2DQrr 0x380000002100d6 +#define FE_MMX_PMOVMSKBrr 0x380000000100d7 +#define FE_MMX_PSUBUSBrm 0x380000000100d8 +#define FE_MMX_PSUBUSBrr 0x380000000100d8 +#define FE_MMX_PSUBUSWrm 0x380000000100d9 +#define FE_MMX_PSUBUSWrr 0x380000000100d9 +#define FE_MMX_PMINUBrm 0x380000000100da +#define FE_MMX_PMINUBrr 0x380000000100da +#define FE_MMX_PANDrm 0x380000000100db +#define FE_MMX_PANDrr 0x380000000100db +#define FE_MMX_PADDUSBrm 0x380000000100dc +#define FE_MMX_PADDUSBrr 0x380000000100dc +#define FE_MMX_PADDUSWrm 0x380000000100dd +#define FE_MMX_PADDUSWrr 0x380000000100dd +#define FE_MMX_PMAXUBrm 0x380000000100de +#define FE_MMX_PMAXUBrr 0x380000000100de +#define FE_MMX_PANDNrm 0x380000000100df +#define FE_MMX_PANDNrr 0x380000000100df +#define FE_MMX_PAVGBrm 0x380000000100e0 +#define FE_MMX_PAVGBrr 0x380000000100e0 +#define FE_MMX_PSRAWrm 0x380000000100e1 +#define FE_MMX_PSRAWrr 0x380000000100e1 +#define FE_MMX_PSRADrm 0x380000000100e2 +#define FE_MMX_PSRADrr 0x380000000100e2 +#define FE_MMX_PAVGWrm 0x380000000100e3 +#define FE_MMX_PAVGWrr 0x380000000100e3 +#define FE_MMX_PMULHUWrm 0x380000000100e4 +#define FE_MMX_PMULHUWrr 0x380000000100e4 +#define FE_MMX_PMULHWrm 0x380000000100e5 +#define FE_MMX_PMULHWrr 0x380000000100e5 +#define FE_MMX_MOVNTQmr 0x300000000100e7 +#define FE_MMX_PSUBSBrm 0x380000000100e8 +#define FE_MMX_PSUBSBrr 0x380000000100e8 +#define FE_MMX_PSUBSWrm 0x380000000100e9 +#define FE_MMX_PSUBSWrr 0x380000000100e9 +#define FE_MMX_PORrm 0x380000000100eb +#define FE_MMX_PORrr 0x380000000100eb +#define FE_MMX_PADDSBrm 0x380000000100ec +#define FE_MMX_PADDSBrr 0x380000000100ec +#define FE_MMX_PMINSWrm 0x380000000100ea +#define FE_MMX_PMINSWrr 0x380000000100ea +#define FE_MMX_PMAXSWrm 0x380000000100ee +#define FE_MMX_PMAXSWrr 0x380000000100ee +#define FE_MMX_PADDSWrm 0x380000000100ed +#define FE_MMX_PADDSWrr 0x380000000100ed +#define FE_MMX_PXORrm 0x380000000100ef +#define FE_MMX_PXORrr 0x380000000100ef +#define FE_MMX_PSLLWrm 0x380000000100f1 +#define FE_MMX_PSLLWrr 0x380000000100f1 +#define FE_MMX_PSLLDrm 0x380000000100f2 +#define FE_MMX_PSLLDrr 0x380000000100f2 +#define FE_MMX_PSLLQrm 0x380000000100f3 +#define FE_MMX_PSLLQrr 0x380000000100f3 +#define FE_MMX_PMULUDQrm 0x380000000100f4 +#define FE_MMX_PMULUDQrr 0x380000000100f4 +#define FE_MMX_PMADDWDrm 0x380000000100f5 +#define FE_MMX_PMADDWDrr 0x380000000100f5 +#define FE_MMX_PSADBWrm 0x380000000100f6 +#define FE_MMX_PSADBWrr 0x380000000100f6 +#define FE_MMX_MASKMOVQrr 0x380000000100f7 +#define FE_MMX_PSUBBrm 0x380000000100f8 +#define FE_MMX_PSUBBrr 0x380000000100f8 +#define FE_MMX_PSUBWrm 0x380000000100f9 +#define FE_MMX_PSUBWrr 0x380000000100f9 +#define FE_MMX_PSUBDrm 0x380000000100fa +#define FE_MMX_PSUBDrr 0x380000000100fa +#define FE_MMX_PSUBQrm 0x380000000100fb +#define FE_MMX_PSUBQrr 0x380000000100fb +#define FE_MMX_PADDBrm 0x380000000100fc +#define FE_MMX_PADDBrr 0x380000000100fc +#define FE_MMX_PADDWrm 0x380000000100fd +#define FE_MMX_PADDWrr 0x380000000100fd +#define FE_MMX_PADDDrm 0x380000000100fe +#define FE_MMX_PADDDrr 0x380000000100fe +#define FE_MMX_PSHUFBrm 0x38000000020000 +#define FE_MMX_PSHUFBrr 0x38000000020000 +#define FE_MMX_PHADDWrm 0x38000000020001 +#define FE_MMX_PHADDWrr 0x38000000020001 +#define FE_MMX_PHADDDrm 0x38000000020002 +#define FE_MMX_PHADDDrr 0x38000000020002 +#define FE_MMX_PHADDSWrm 0x38000000020003 +#define FE_MMX_PHADDSWrr 0x38000000020003 +#define FE_MMX_PMADDUBSWrm 0x38000000020004 +#define FE_MMX_PMADDUBSWrr 0x38000000020004 +#define FE_MMX_PHSUBWrm 0x38000000020005 +#define FE_MMX_PHSUBWrr 0x38000000020005 +#define FE_MMX_PHSUBDrm 0x38000000020006 +#define FE_MMX_PHSUBDrr 0x38000000020006 +#define FE_MMX_PHSUBSWrm 0x38000000020007 +#define FE_MMX_PHSUBSWrr 0x38000000020007 +#define FE_MMX_PSIGNBrm 0x38000000020008 +#define FE_MMX_PSIGNBrr 0x38000000020008 +#define FE_MMX_PSIGNWrm 0x38000000020009 +#define FE_MMX_PSIGNWrr 0x38000000020009 +#define FE_MMX_PSIGNDrm 0x3800000002000a +#define FE_MMX_PSIGNDrr 0x3800000002000a +#define FE_MMX_PMULHRSWrm 0x3800000002000b +#define FE_MMX_PMULHRSWrr 0x3800000002000b +#define FE_MMX_PABSBrm 0x3800000002001c +#define FE_MMX_PABSBrr 0x3800000002001c +#define FE_MMX_PABSWrm 0x3800000002001d +#define FE_MMX_PABSWrr 0x3800000002001d +#define FE_MMX_PABSDrm 0x3800000002001e +#define FE_MMX_PABSDrr 0x3800000002001e +#define FE_MMX_PALIGNRrmi 0x5080000003000f +#define FE_MMX_PALIGNRrri 0x5080000003000f +#define FE_SSE_MOVUPSrm 0x38000000010010 +#define FE_SSE_MOVUPSrr 0x38000000010010 +#define FE_SSE_MOVUPDrm 0x38000000090010 +#define FE_SSE_MOVUPDrr 0x38000000090010 +#define FE_SSE_MOVSSrm 0x38000000210010 +#define FE_SSE_MOVSSrr 0x38000000210010 +#define FE_SSE_MOVSDrm 0x38000000110010 +#define FE_SSE_MOVSDrr 0x38000000110010 +#define FE_SSE_MOVUPSmr 0x30000000010011 +#define FE_SSE_MOVUPDmr 0x30000000090011 +#define FE_SSE_MOVSSmr 0x30000000210011 +#define FE_SSE_MOVSDmr 0x30000000110011 +#define FE_SSE_MOVLPSrm 0x38000000010012 +#define FE_SSE_MOVHLPSrr 0x38000000010012 +#define FE_SSE_MOVLPDrm 0x38000000090012 +#define FE_SSE_MOVSLDUPrm 0x38000000210012 +#define FE_SSE_MOVSLDUPrr 0x38000000210012 +#define FE_SSE_MOVDDUPrm 0x38000000110012 +#define FE_SSE_MOVDDUPrr 0x38000000110012 +#define FE_SSE_MOVLPSmr 0x30000000010013 +#define FE_SSE_MOVLPDmr 0x30000000090013 +#define FE_SSE_UNPCKLPSrm 0x38000000010014 +#define FE_SSE_UNPCKLPSrr 0x38000000010014 +#define FE_SSE_UNPCKLPDrm 0x38000000090014 +#define FE_SSE_UNPCKLPDrr 0x38000000090014 +#define FE_SSE_UNPCKHPSrm 0x38000000010015 +#define FE_SSE_UNPCKHPSrr 0x38000000010015 +#define FE_SSE_UNPCKHPDrm 0x38000000090015 +#define FE_SSE_UNPCKHPDrr 0x38000000090015 +#define FE_SSE_MOVHPSrm 0x38000000010016 +#define FE_SSE_MOVLHPSrr 0x38000000010016 +#define FE_SSE_MOVHPDrm 0x38000000090016 +#define FE_SSE_MOVSHDUPrm 0x38000000210016 +#define FE_SSE_MOVSHDUPrr 0x38000000210016 +#define FE_SSE_MOVHPSmr 0x30000000010017 +#define FE_SSE_MOVHPDmr 0x30000000090017 +#define FE_SSE_MOVAPSrm 0x38000000010028 +#define FE_SSE_MOVAPSrr 0x38000000010028 +#define FE_SSE_MOVAPDrm 0x38000000090028 +#define FE_SSE_MOVAPDrr 0x38000000090028 +#define FE_SSE_MOVAPSmr 0x30000000010029 +#define FE_SSE_MOVAPDmr 0x30000000090029 +#define FE_SSE_CVTSI2SS32rm 0x3800000021002a +#define FE_SSE_CVTSI2SS32rr 0x3800000021002a +#define FE_SSE_CVTSI2SS64rm 0x3800000061002a +#define FE_SSE_CVTSI2SS64rr 0x3800000061002a +#define FE_SSE_CVTSI2SD32rm 0x3800000011002a +#define FE_SSE_CVTSI2SD32rr 0x3800000011002a +#define FE_SSE_CVTSI2SD64rm 0x3800000051002a +#define FE_SSE_CVTSI2SD64rr 0x3800000051002a +#define FE_SSE_MOVNTPSmr 0x3000000001002b +#define FE_SSE_MOVNTPDmr 0x3000000009002b +#define FE_SSE_MOVNTSSmr 0x3000000021002b +#define FE_SSE_MOVNTSDmr 0x3000000011002b +#define FE_SSE_CVTTSS2SI32rm 0x3800000021002c +#define FE_SSE_CVTTSS2SI32rr 0x3800000021002c +#define FE_SSE_CVTTSS2SI64rm 0x3800000061002c +#define FE_SSE_CVTTSS2SI64rr 0x3800000061002c +#define FE_SSE_CVTTSD2SI32rm 0x3800000011002c +#define FE_SSE_CVTTSD2SI32rr 0x3800000011002c +#define FE_SSE_CVTTSD2SI64rm 0x3800000051002c +#define FE_SSE_CVTTSD2SI64rr 0x3800000051002c +#define FE_SSE_CVTSS2SI32rm 0x3800000021002d +#define FE_SSE_CVTSS2SI32rr 0x3800000021002d +#define FE_SSE_CVTSS2SI64rm 0x3800000061002d +#define FE_SSE_CVTSS2SI64rr 0x3800000061002d +#define FE_SSE_CVTSD2SI32rm 0x3800000011002d +#define FE_SSE_CVTSD2SI32rr 0x3800000011002d +#define FE_SSE_CVTSD2SI64rm 0x3800000051002d +#define FE_SSE_CVTSD2SI64rr 0x3800000051002d +#define FE_SSE_UCOMISSrm 0x3800000001002e +#define FE_SSE_UCOMISSrr 0x3800000001002e +#define FE_SSE_UCOMISDrm 0x3800000009002e +#define FE_SSE_UCOMISDrr 0x3800000009002e +#define FE_SSE_COMISSrm 0x3800000001002f +#define FE_SSE_COMISSrr 0x3800000001002f +#define FE_SSE_COMISDrm 0x3800000009002f +#define FE_SSE_COMISDrr 0x3800000009002f +#define FE_SSE_MOVMSKPSrr 0x38000000010050 +#define FE_SSE_MOVMSKPDrr 0x38000000090050 +#define FE_SSE_SQRTPSrm 0x38000000010051 +#define FE_SSE_SQRTPSrr 0x38000000010051 +#define FE_SSE_SQRTPDrm 0x38000000090051 +#define FE_SSE_SQRTPDrr 0x38000000090051 +#define FE_SSE_SQRTSSrm 0x38000000210051 +#define FE_SSE_SQRTSSrr 0x38000000210051 +#define FE_SSE_SQRTSDrm 0x38000000110051 +#define FE_SSE_SQRTSDrr 0x38000000110051 +#define FE_SSE_RSQRTPSrm 0x38000000010052 +#define FE_SSE_RSQRTPSrr 0x38000000010052 +#define FE_SSE_RSQRTSSrm 0x38000000210052 +#define FE_SSE_RSQRTSSrr 0x38000000210052 +#define FE_SSE_RCPPSrm 0x38000000010053 +#define FE_SSE_RCPPSrr 0x38000000010053 +#define FE_SSE_RCPSSrm 0x38000000210053 +#define FE_SSE_RCPSSrr 0x38000000210053 +#define FE_SSE_ANDPSrm 0x38000000010054 +#define FE_SSE_ANDPSrr 0x38000000010054 +#define FE_SSE_ANDPDrm 0x38000000090054 +#define FE_SSE_ANDPDrr 0x38000000090054 +#define FE_SSE_ANDNPSrm 0x38000000010055 +#define FE_SSE_ANDNPSrr 0x38000000010055 +#define FE_SSE_ANDNPDrm 0x38000000090055 +#define FE_SSE_ANDNPDrr 0x38000000090055 +#define FE_SSE_ORPSrm 0x38000000010056 +#define FE_SSE_ORPSrr 0x38000000010056 +#define FE_SSE_ORPDrm 0x38000000090056 +#define FE_SSE_ORPDrr 0x38000000090056 +#define FE_SSE_XORPSrm 0x38000000010057 +#define FE_SSE_XORPSrr 0x38000000010057 +#define FE_SSE_XORPDrm 0x38000000090057 +#define FE_SSE_XORPDrr 0x38000000090057 +#define FE_SSE_ADDPSrm 0x38000000010058 +#define FE_SSE_ADDPSrr 0x38000000010058 +#define FE_SSE_ADDPDrm 0x38000000090058 +#define FE_SSE_ADDPDrr 0x38000000090058 +#define FE_SSE_ADDSSrm 0x38000000210058 +#define FE_SSE_ADDSSrr 0x38000000210058 +#define FE_SSE_ADDSDrm 0x38000000110058 +#define FE_SSE_ADDSDrr 0x38000000110058 +#define FE_SSE_MULPSrm 0x38000000010059 +#define FE_SSE_MULPSrr 0x38000000010059 +#define FE_SSE_MULPDrm 0x38000000090059 +#define FE_SSE_MULPDrr 0x38000000090059 +#define FE_SSE_MULSSrm 0x38000000210059 +#define FE_SSE_MULSSrr 0x38000000210059 +#define FE_SSE_MULSDrm 0x38000000110059 +#define FE_SSE_MULSDrr 0x38000000110059 +#define FE_SSE_CVTPS2PDrm 0x3800000001005a +#define FE_SSE_CVTPS2PDrr 0x3800000001005a +#define FE_SSE_CVTPD2PSrm 0x3800000009005a +#define FE_SSE_CVTPD2PSrr 0x3800000009005a +#define FE_SSE_CVTSS2SDrm 0x3800000021005a +#define FE_SSE_CVTSS2SDrr 0x3800000021005a +#define FE_SSE_CVTSD2SSrm 0x3800000011005a +#define FE_SSE_CVTSD2SSrr 0x3800000011005a +#define FE_SSE_CVTDQ2PSrm 0x3800000001005b +#define FE_SSE_CVTDQ2PSrr 0x3800000001005b +#define FE_SSE_CVTPS2DQrm 0x3800000009005b +#define FE_SSE_CVTPS2DQrr 0x3800000009005b +#define FE_SSE_CVTTPS2DQrm 0x3800000021005b +#define FE_SSE_CVTTPS2DQrr 0x3800000021005b +#define FE_SSE_SUBPSrm 0x3800000001005c +#define FE_SSE_SUBPSrr 0x3800000001005c +#define FE_SSE_SUBPDrm 0x3800000009005c +#define FE_SSE_SUBPDrr 0x3800000009005c +#define FE_SSE_SUBSSrm 0x3800000021005c +#define FE_SSE_SUBSSrr 0x3800000021005c +#define FE_SSE_SUBSDrm 0x3800000011005c +#define FE_SSE_SUBSDrr 0x3800000011005c +#define FE_SSE_MINPSrm 0x3800000001005d +#define FE_SSE_MINPSrr 0x3800000001005d +#define FE_SSE_MINPDrm 0x3800000009005d +#define FE_SSE_MINPDrr 0x3800000009005d +#define FE_SSE_MINSSrm 0x3800000021005d +#define FE_SSE_MINSSrr 0x3800000021005d +#define FE_SSE_MINSDrm 0x3800000011005d +#define FE_SSE_MINSDrr 0x3800000011005d +#define FE_SSE_DIVPSrm 0x3800000001005e +#define FE_SSE_DIVPSrr 0x3800000001005e +#define FE_SSE_DIVPDrm 0x3800000009005e +#define FE_SSE_DIVPDrr 0x3800000009005e +#define FE_SSE_DIVSSrm 0x3800000021005e +#define FE_SSE_DIVSSrr 0x3800000021005e +#define FE_SSE_DIVSDrm 0x3800000011005e +#define FE_SSE_DIVSDrr 0x3800000011005e +#define FE_SSE_MAXPSrm 0x3800000001005f +#define FE_SSE_MAXPSrr 0x3800000001005f +#define FE_SSE_MAXPDrm 0x3800000009005f +#define FE_SSE_MAXPDrr 0x3800000009005f +#define FE_SSE_MAXSSrm 0x3800000021005f +#define FE_SSE_MAXSSrr 0x3800000021005f +#define FE_SSE_MAXSDrm 0x3800000011005f +#define FE_SSE_MAXSDrr 0x3800000011005f +#define FE_SSE_PUNPCKLBWrm 0x38000000090060 +#define FE_SSE_PUNPCKLBWrr 0x38000000090060 +#define FE_SSE_PUNPCKLWDrm 0x38000000090061 +#define FE_SSE_PUNPCKLWDrr 0x38000000090061 +#define FE_SSE_PUNPCKLDQrm 0x38000000090062 +#define FE_SSE_PUNPCKLDQrr 0x38000000090062 +#define FE_SSE_PACKSSWBrm 0x38000000090063 +#define FE_SSE_PACKSSWBrr 0x38000000090063 +#define FE_SSE_PCMPGTBrm 0x38000000090064 +#define FE_SSE_PCMPGTBrr 0x38000000090064 +#define FE_SSE_PCMPGTWrm 0x38000000090065 +#define FE_SSE_PCMPGTWrr 0x38000000090065 +#define FE_SSE_PCMPGTDrm 0x38000000090066 +#define FE_SSE_PCMPGTDrr 0x38000000090066 +#define FE_SSE_PACKUSWBrm 0x38000000090067 +#define FE_SSE_PACKUSWBrr 0x38000000090067 +#define FE_SSE_PUNPCKHBWrm 0x38000000090068 +#define FE_SSE_PUNPCKHBWrr 0x38000000090068 +#define FE_SSE_PUNPCKHWDrm 0x38000000090069 +#define FE_SSE_PUNPCKHWDrr 0x38000000090069 +#define FE_SSE_PUNPCKHDQrm 0x3800000009006a +#define FE_SSE_PUNPCKHDQrr 0x3800000009006a +#define FE_SSE_PACKSSDWrm 0x3800000009006b +#define FE_SSE_PACKSSDWrr 0x3800000009006b +#define FE_SSE_PUNPCKLQDQrm 0x3800000009006c +#define FE_SSE_PUNPCKLQDQrr 0x3800000009006c +#define FE_SSE_PUNPCKHQDQrm 0x3800000009006d +#define FE_SSE_PUNPCKHQDQrr 0x3800000009006d +#define FE_SSE_MOVD_G2Xrm 0x3800000009006e +#define FE_SSE_MOVD_G2Xrr 0x3800000009006e +#define FE_SSE_MOVQ_G2Xrm 0x3800000049006e +#define FE_SSE_MOVQ_G2Xrr 0x3800000049006e +#define FE_SSE_MOVDQArm 0x3800000009006f +#define FE_SSE_MOVDQArr 0x3800000009006f +#define FE_SSE_MOVDQUrm 0x3800000021006f +#define FE_SSE_MOVDQUrr 0x3800000021006f +#define FE_SSE_PSHUFDrmi 0x50800000090070 +#define FE_SSE_PSHUFDrri 0x50800000090070 +#define FE_SSE_PSHUFHWrmi 0x50800000210070 +#define FE_SSE_PSHUFHWrri 0x50800000210070 +#define FE_SSE_PSHUFLWrmi 0x50800000110070 +#define FE_SSE_PSHUFLWrri 0x50800000110070 +#define FE_SSE_PSRLWri 0x20800000090271 +#define FE_SSE_PSRAWri 0x20800000090471 +#define FE_SSE_PSLLWri 0x20800000090671 +#define FE_SSE_PSRLDri 0x20800000090272 +#define FE_SSE_PSRADri 0x20800000090472 +#define FE_SSE_PSLLDri 0x20800000090672 +#define FE_SSE_PSRLQri 0x20800000090273 +#define FE_SSE_PSRLDQri 0x20800000090373 +#define FE_SSE_PSLLQri 0x20800000090673 +#define FE_SSE_PSLLDQri 0x20800000090773 +#define FE_SSE_PCMPEQBrm 0x38000000090074 +#define FE_SSE_PCMPEQBrr 0x38000000090074 +#define FE_SSE_PCMPEQWrm 0x38000000090075 +#define FE_SSE_PCMPEQWrr 0x38000000090075 +#define FE_SSE_PCMPEQDrm 0x38000000090076 +#define FE_SSE_PCMPEQDrr 0x38000000090076 +#define FE_SSE_EXTRQri 0x21000000090078 +#define FE_SSE_INSERTQrri 0x51000000110078 +#define FE_SSE_EXTRQrr 0x38000000090079 +#define FE_SSE_INSERTQrr 0x38000000110079 +#define FE_SSE_HADDPDrm 0x3800000009007c +#define FE_SSE_HADDPDrr 0x3800000009007c +#define FE_SSE_HADDPSrm 0x3800000011007c +#define FE_SSE_HADDPSrr 0x3800000011007c +#define FE_SSE_HSUBPDrm 0x3800000009007d +#define FE_SSE_HSUBPDrr 0x3800000009007d +#define FE_SSE_HSUBPSrm 0x3800000011007d +#define FE_SSE_HSUBPSrr 0x3800000011007d +#define FE_SSE_MOVD_X2Gmr 0x3000000009007e +#define FE_SSE_MOVD_X2Grr 0x3000000009007e +#define FE_SSE_MOVQ_X2Gmr 0x3000000049007e +#define FE_SSE_MOVQ_X2Grr 0x3000000049007e +#define FE_SSE_MOVQrm 0x3800000021007e +#define FE_SSE_MOVQrr 0x3800000021007e +#define FE_SSE_MOVDQAmr 0x3000000009007f +#define FE_SSE_MOVDQUmr 0x3000000021007f +#define FE_FXSAVE32m 0x100000000100ae +#define FE_FXSAVE64m 0x100000004100ae +#define FE_FXRSTOR32m 0x100000000101ae +#define FE_FXRSTOR64m 0x100000004101ae +#define FE_LDMXCSRm 0x100000000102ae +#define FE_STMXCSRm 0x100000000103ae +#define FE_LFENCE 0x800000001e8ae +#define FE_MFENCE 0x800000001f0ae +#define FE_SFENCE 0x800000001f8ae +#define FE_SSE_CMPPSrmi 0x508000000100c2 +#define FE_SSE_CMPPSrri 0x508000000100c2 +#define FE_SSE_CMPPDrmi 0x508000000900c2 +#define FE_SSE_CMPPDrri 0x508000000900c2 +#define FE_SSE_CMPSSrmi 0x508000002100c2 +#define FE_SSE_CMPSSrri 0x508000002100c2 +#define FE_SSE_CMPSDrmi 0x508000001100c2 +#define FE_SSE_CMPSDrri 0x508000001100c2 +#define FE_SSE_PINSRWrmi 0x508000000900c4 +#define FE_SSE_PINSRWrri 0x508000000900c4 +#define FE_SSE_PEXTRWrri 0x508000000900c5 +#define FE_SSE_SHUFPSrmi 0x508000000100c6 +#define FE_SSE_SHUFPSrri 0x508000000100c6 +#define FE_SSE_SHUFPDrmi 0x508000000900c6 +#define FE_SSE_SHUFPDrri 0x508000000900c6 +#define FE_SSE_ADDSUBPDrm 0x380000000900d0 +#define FE_SSE_ADDSUBPDrr 0x380000000900d0 +#define FE_SSE_ADDSUBPSrm 0x380000001100d0 +#define FE_SSE_ADDSUBPSrr 0x380000001100d0 +#define FE_SSE_PSRLWrm 0x380000000900d1 +#define FE_SSE_PSRLWrr 0x380000000900d1 +#define FE_SSE_PSRLDrm 0x380000000900d2 +#define FE_SSE_PSRLDrr 0x380000000900d2 +#define FE_SSE_PSRLQrm 0x380000000900d3 +#define FE_SSE_PSRLQrr 0x380000000900d3 +#define FE_SSE_PADDQrm 0x380000000900d4 +#define FE_SSE_PADDQrr 0x380000000900d4 +#define FE_SSE_PMULLWrm 0x380000000900d5 +#define FE_SSE_PMULLWrr 0x380000000900d5 +#define FE_SSE_MOVQmr 0x300000000900d6 +#define FE_SSE_PMOVMSKBrr 0x380000000900d7 +#define FE_SSE_PSUBUSBrm 0x380000000900d8 +#define FE_SSE_PSUBUSBrr 0x380000000900d8 +#define FE_SSE_PSUBUSWrm 0x380000000900d9 +#define FE_SSE_PSUBUSWrr 0x380000000900d9 +#define FE_SSE_PMINUBrm 0x380000000900da +#define FE_SSE_PMINUBrr 0x380000000900da +#define FE_SSE_PANDrm 0x380000000900db +#define FE_SSE_PANDrr 0x380000000900db +#define FE_SSE_PADDUSBrm 0x380000000900dc +#define FE_SSE_PADDUSBrr 0x380000000900dc +#define FE_SSE_PADDUSWrm 0x380000000900dd +#define FE_SSE_PADDUSWrr 0x380000000900dd +#define FE_SSE_PMAXUBrm 0x380000000900de +#define FE_SSE_PMAXUBrr 0x380000000900de +#define FE_SSE_PANDNrm 0x380000000900df +#define FE_SSE_PANDNrr 0x380000000900df +#define FE_SSE_PAVGBrm 0x380000000900e0 +#define FE_SSE_PAVGBrr 0x380000000900e0 +#define FE_SSE_PSRAWrm 0x380000000900e1 +#define FE_SSE_PSRAWrr 0x380000000900e1 +#define FE_SSE_PSRADrm 0x380000000900e2 +#define FE_SSE_PSRADrr 0x380000000900e2 +#define FE_SSE_PAVGWrm 0x380000000900e3 +#define FE_SSE_PAVGWrr 0x380000000900e3 +#define FE_SSE_PMULHUWrm 0x380000000900e4 +#define FE_SSE_PMULHUWrr 0x380000000900e4 +#define FE_SSE_PMULHWrm 0x380000000900e5 +#define FE_SSE_PMULHWrr 0x380000000900e5 +#define FE_SSE_CVTTPD2DQrm 0x380000000900e6 +#define FE_SSE_CVTTPD2DQrr 0x380000000900e6 +#define FE_SSE_CVTDQ2PDrm 0x380000002100e6 +#define FE_SSE_CVTDQ2PDrr 0x380000002100e6 +#define FE_SSE_CVTPD2DQrm 0x380000001100e6 +#define FE_SSE_CVTPD2DQrr 0x380000001100e6 +#define FE_SSE_MOVNTDQmr 0x300000000900e7 +#define FE_SSE_PSUBSBrm 0x380000000900e8 +#define FE_SSE_PSUBSBrr 0x380000000900e8 +#define FE_SSE_PSUBSWrm 0x380000000900e9 +#define FE_SSE_PSUBSWrr 0x380000000900e9 +#define FE_SSE_PORrm 0x380000000900eb +#define FE_SSE_PORrr 0x380000000900eb +#define FE_SSE_PADDSBrm 0x380000000900ec +#define FE_SSE_PADDSBrr 0x380000000900ec +#define FE_SSE_PMINSWrm 0x380000000900ea +#define FE_SSE_PMINSWrr 0x380000000900ea +#define FE_SSE_PMAXSWrm 0x380000000900ee +#define FE_SSE_PMAXSWrr 0x380000000900ee +#define FE_SSE_PADDSWrm 0x380000000900ed +#define FE_SSE_PADDSWrr 0x380000000900ed +#define FE_SSE_PXORrm 0x380000000900ef +#define FE_SSE_PXORrr 0x380000000900ef +#define FE_SSE_LDDQUrm 0x380000001100f0 +#define FE_SSE_PSLLWrm 0x380000000900f1 +#define FE_SSE_PSLLWrr 0x380000000900f1 +#define FE_SSE_PSLLDrm 0x380000000900f2 +#define FE_SSE_PSLLDrr 0x380000000900f2 +#define FE_SSE_PSLLQrm 0x380000000900f3 +#define FE_SSE_PSLLQrr 0x380000000900f3 +#define FE_SSE_PMULUDQrm 0x380000000900f4 +#define FE_SSE_PMULUDQrr 0x380000000900f4 +#define FE_SSE_PMADDWDrm 0x380000000900f5 +#define FE_SSE_PMADDWDrr 0x380000000900f5 +#define FE_SSE_PSADBWrm 0x380000000900f6 +#define FE_SSE_PSADBWrr 0x380000000900f6 +#define FE_SSE_MASKMOVDQUrr 0x380000000900f7 +#define FE_SSE_PSUBBrm 0x380000000900f8 +#define FE_SSE_PSUBBrr 0x380000000900f8 +#define FE_SSE_PSUBWrm 0x380000000900f9 +#define FE_SSE_PSUBWrr 0x380000000900f9 +#define FE_SSE_PSUBDrm 0x380000000900fa +#define FE_SSE_PSUBDrr 0x380000000900fa +#define FE_SSE_PSUBQrm 0x380000000900fb +#define FE_SSE_PSUBQrr 0x380000000900fb +#define FE_SSE_PADDBrm 0x380000000900fc +#define FE_SSE_PADDBrr 0x380000000900fc +#define FE_SSE_PADDWrm 0x380000000900fd +#define FE_SSE_PADDWrr 0x380000000900fd +#define FE_SSE_PADDDrm 0x380000000900fe +#define FE_SSE_PADDDrr 0x380000000900fe +#define FE_SSE_PSHUFBrm 0x380000000a0000 +#define FE_SSE_PSHUFBrr 0x380000000a0000 +#define FE_SSE_PHADDWrm 0x380000000a0001 +#define FE_SSE_PHADDWrr 0x380000000a0001 +#define FE_SSE_PHADDDrm 0x380000000a0002 +#define FE_SSE_PHADDDrr 0x380000000a0002 +#define FE_SSE_PHADDSWrm 0x380000000a0003 +#define FE_SSE_PHADDSWrr 0x380000000a0003 +#define FE_SSE_PMADDUBSWrm 0x380000000a0004 +#define FE_SSE_PMADDUBSWrr 0x380000000a0004 +#define FE_SSE_PHSUBWrm 0x380000000a0005 +#define FE_SSE_PHSUBWrr 0x380000000a0005 +#define FE_SSE_PHSUBDrm 0x380000000a0006 +#define FE_SSE_PHSUBDrr 0x380000000a0006 +#define FE_SSE_PHSUBSWrm 0x380000000a0007 +#define FE_SSE_PHSUBSWrr 0x380000000a0007 +#define FE_SSE_PSIGNBrm 0x380000000a0008 +#define FE_SSE_PSIGNBrr 0x380000000a0008 +#define FE_SSE_PSIGNWrm 0x380000000a0009 +#define FE_SSE_PSIGNWrr 0x380000000a0009 +#define FE_SSE_PSIGNDrm 0x380000000a000a +#define FE_SSE_PSIGNDrr 0x380000000a000a +#define FE_SSE_PMULHRSWrm 0x380000000a000b +#define FE_SSE_PMULHRSWrr 0x380000000a000b +#define FE_SSE_PBLENDVBrm 0x380000000a0010 +#define FE_SSE_PBLENDVBrr 0x380000000a0010 +#define FE_SSE_BLENDVPSrmr 0x400000000a0014 +#define FE_SSE_BLENDVPSrrr 0x400000000a0014 +#define FE_SSE_BLENDVPDrmr 0x400000000a0015 +#define FE_SSE_BLENDVPDrrr 0x400000000a0015 +#define FE_SSE_PTESTrm 0x380000000a0017 +#define FE_SSE_PTESTrr 0x380000000a0017 +#define FE_SSE_PABSBrm 0x380000000a001c +#define FE_SSE_PABSBrr 0x380000000a001c +#define FE_SSE_PABSWrm 0x380000000a001d +#define FE_SSE_PABSWrr 0x380000000a001d +#define FE_SSE_PABSDrm 0x380000000a001e +#define FE_SSE_PABSDrr 0x380000000a001e +#define FE_SSE_PMOVSXBWrm 0x380000000a0020 +#define FE_SSE_PMOVSXBWrr 0x380000000a0020 +#define FE_SSE_PMOVSXBDrm 0x380000000a0021 +#define FE_SSE_PMOVSXBDrr 0x380000000a0021 +#define FE_SSE_PMOVSXBQrm 0x380000000a0022 +#define FE_SSE_PMOVSXBQrr 0x380000000a0022 +#define FE_SSE_PMOVSXWDrm 0x380000000a0023 +#define FE_SSE_PMOVSXWDrr 0x380000000a0023 +#define FE_SSE_PMOVSXWQrm 0x380000000a0024 +#define FE_SSE_PMOVSXWQrr 0x380000000a0024 +#define FE_SSE_PMOVSXDQrm 0x380000000a0025 +#define FE_SSE_PMOVSXDQrr 0x380000000a0025 +#define FE_SSE_PMULDQrm 0x380000000a0028 +#define FE_SSE_PMULDQrr 0x380000000a0028 +#define FE_SSE_PCMPEQQrm 0x380000000a0029 +#define FE_SSE_PCMPEQQrr 0x380000000a0029 +#define FE_SSE_MOVNTDQArm 0x380000000a002a +#define FE_SSE_PACKUSDWrm 0x380000000a002b +#define FE_SSE_PACKUSDWrr 0x380000000a002b +#define FE_SSE_PMOVZXBWrm 0x380000000a0030 +#define FE_SSE_PMOVZXBWrr 0x380000000a0030 +#define FE_SSE_PMOVZXBDrm 0x380000000a0031 +#define FE_SSE_PMOVZXBDrr 0x380000000a0031 +#define FE_SSE_PMOVZXBQrm 0x380000000a0032 +#define FE_SSE_PMOVZXBQrr 0x380000000a0032 +#define FE_SSE_PMOVZXWDrm 0x380000000a0033 +#define FE_SSE_PMOVZXWDrr 0x380000000a0033 +#define FE_SSE_PMOVZXWQrm 0x380000000a0034 +#define FE_SSE_PMOVZXWQrr 0x380000000a0034 +#define FE_SSE_PMOVZXDQrm 0x380000000a0035 +#define FE_SSE_PMOVZXDQrr 0x380000000a0035 +#define FE_SSE_PCMPGTQrm 0x380000000a0037 +#define FE_SSE_PCMPGTQrr 0x380000000a0037 +#define FE_SSE_PMINSBrm 0x380000000a0038 +#define FE_SSE_PMINSBrr 0x380000000a0038 +#define FE_SSE_PMINSDrm 0x380000000a0039 +#define FE_SSE_PMINSDrr 0x380000000a0039 +#define FE_SSE_PMINUWrm 0x380000000a003a +#define FE_SSE_PMINUWrr 0x380000000a003a +#define FE_SSE_PMINUDrm 0x380000000a003b +#define FE_SSE_PMINUDrr 0x380000000a003b +#define FE_SSE_PMAXSBrm 0x380000000a003c +#define FE_SSE_PMAXSBrr 0x380000000a003c +#define FE_SSE_PMAXSDrm 0x380000000a003d +#define FE_SSE_PMAXSDrr 0x380000000a003d +#define FE_SSE_PMAXUWrm 0x380000000a003e +#define FE_SSE_PMAXUWrr 0x380000000a003e +#define FE_SSE_PMAXUDrm 0x380000000a003f +#define FE_SSE_PMAXUDrr 0x380000000a003f +#define FE_SSE_PMULLDrm 0x380000000a0040 +#define FE_SSE_PMULLDrr 0x380000000a0040 +#define FE_SSE_PHMINPOSUWrm 0x380000000a0041 +#define FE_SSE_PHMINPOSUWrr 0x380000000a0041 +#define FE_MOVDIR64Brm 0x380000000a00f8 +#define FE_MOVDIRI32mr 0x300000000200f9 +#define FE_MOVDIRI64mr 0x300000004200f9 +#define FE_SSE_ROUNDPSrmi 0x508000000b0008 +#define FE_SSE_ROUNDPSrri 0x508000000b0008 +#define FE_SSE_ROUNDPDrmi 0x508000000b0009 +#define FE_SSE_ROUNDPDrri 0x508000000b0009 +#define FE_SSE_ROUNDSSrmi 0x508000000b000a +#define FE_SSE_ROUNDSSrri 0x508000000b000a +#define FE_SSE_ROUNDSDrmi 0x508000000b000b +#define FE_SSE_ROUNDSDrri 0x508000000b000b +#define FE_SSE_BLENDPSrmi 0x508000000b000c +#define FE_SSE_BLENDPSrri 0x508000000b000c +#define FE_SSE_BLENDPDrmi 0x508000000b000d +#define FE_SSE_BLENDPDrri 0x508000000b000d +#define FE_SSE_PBLENDWrmi 0x508000000b000e +#define FE_SSE_PBLENDWrri 0x508000000b000e +#define FE_SSE_PALIGNRrmi 0x508000000b000f +#define FE_SSE_PALIGNRrri 0x508000000b000f +#define FE_SSE_PEXTRBmri 0x488000000b0014 +#define FE_SSE_PEXTRBrri 0x488000000b0014 +#define FE_SSE_PEXTRWmri 0x488000000b0015 +#define FE_SSE_PEXTRDrri 0x488000000b0016 +#define FE_SSE_PEXTRDmri 0x488000000b0016 +#define FE_SSE_PEXTRQrri 0x488000004b0016 +#define FE_SSE_PEXTRQmri 0x488000004b0016 +#define FE_SSE_EXTRACTPSrri 0x488000000b0017 +#define FE_SSE_EXTRACTPSmri 0x488000000b0017 +#define FE_SSE_PINSRBrmi 0x508000000b0020 +#define FE_SSE_PINSRBrri 0x508000000b0020 +#define FE_SSE_INSERTPSrmi 0x508000000b0021 +#define FE_SSE_INSERTPSrri 0x508000000b0021 +#define FE_SSE_PINSRDrmi 0x508000000b0022 +#define FE_SSE_PINSRDrri 0x508000000b0022 +#define FE_SSE_PINSRQrmi 0x508000004b0022 +#define FE_SSE_PINSRQrri 0x508000004b0022 +#define FE_SSE_DPPSrmi 0x508000000b0040 +#define FE_SSE_DPPSrri 0x508000000b0040 +#define FE_SSE_DPPDrmi 0x508000000b0041 +#define FE_SSE_DPPDrri 0x508000000b0041 +#define FE_SSE_MPSADBWrmi 0x508000000b0042 +#define FE_SSE_MPSADBWrri 0x508000000b0042 +#define FE_SSE_PCLMULQDQrmi 0x508000000b0044 +#define FE_SSE_PCLMULQDQrri 0x508000000b0044 +#define FE_SSE_PCMPESTRMrmi 0x508000000b0060 +#define FE_SSE_PCMPESTRMrri 0x508000000b0060 +#define FE_SSE_PCMPESTRIrmi 0x508000000b0061 +#define FE_SSE_PCMPESTRIrri 0x508000000b0061 +#define FE_SSE_PCMPISTRMrmi 0x508000000b0062 +#define FE_SSE_PCMPISTRMrri 0x508000000b0062 +#define FE_SSE_PCMPISTRIrmi 0x508000000b0063 +#define FE_SSE_PCMPISTRIrri 0x508000000b0063 +#define FE_AESIMCrm 0x380000000a00db +#define FE_AESIMCrr 0x380000000a00db +#define FE_AESENCrm 0x380000000a00dc +#define FE_AESENCrr 0x380000000a00dc +#define FE_AESENCLASTrm 0x380000000a00dd +#define FE_AESENCLASTrr 0x380000000a00dd +#define FE_AESDECrm 0x380000000a00de +#define FE_AESDECrr 0x380000000a00de +#define FE_AESDECLASTrm 0x380000000a00df +#define FE_AESDECLASTrr 0x380000000a00df +#define FE_AESKEYGENASSISTrmi 0x508000000b00df +#define FE_AESKEYGENASSISTrri 0x508000000b00df +#define FE_VAESIMCrm 0x380000010a00db +#define FE_VAESIMCrr 0x380000010a00db +#define FE_VAESENC128rrr 0xc00000010a00dc +#define FE_VAESENC128rrm 0xc00000010a00dc +#define FE_VAESENC256rrr 0xc00000018a00dc +#define FE_VAESENC256rrm 0xc00000018a00dc +#define FE_VAESENCLAST128rrr 0xc00000010a00dd +#define FE_VAESENCLAST128rrm 0xc00000010a00dd +#define FE_VAESENCLAST256rrr 0xc00000018a00dd +#define FE_VAESENCLAST256rrm 0xc00000018a00dd +#define FE_VAESDEC128rrr 0xc00000010a00de +#define FE_VAESDEC128rrm 0xc00000010a00de +#define FE_VAESDEC256rrr 0xc00000018a00de +#define FE_VAESDEC256rrm 0xc00000018a00de +#define FE_VAESDECLAST128rrr 0xc00000010a00df +#define FE_VAESDECLAST128rrm 0xc00000010a00df +#define FE_VAESDECLAST256rrr 0xc00000018a00df +#define FE_VAESDECLAST256rrm 0xc00000018a00df +#define FE_VAESKEYGENASSISTrmi 0x508000010b00df +#define FE_VAESKEYGENASSISTrri 0x508000010b00df +#define FE_VMOVUPS128rm 0x38000001010010 +#define FE_VMOVUPS128rr 0x38000001010010 +#define FE_VMOVUPS256rm 0x38000001810010 +#define FE_VMOVUPS256rr 0x38000001810010 +#define FE_VMOVUPD128rm 0x38000001090010 +#define FE_VMOVUPD128rr 0x38000001090010 +#define FE_VMOVUPD256rm 0x38000001890010 +#define FE_VMOVUPD256rr 0x38000001890010 +#define FE_VMOVSSrm 0x38000001210010 +#define FE_VMOVSSrrr 0xc0000001210010 +#define FE_VMOVSDrm 0x38000001110010 +#define FE_VMOVSDrrr 0xc0000001110010 +#define FE_VMOVUPS128mr 0x30000001010011 +#define FE_VMOVUPS256mr 0x30000001810011 +#define FE_VMOVUPD128mr 0x30000001090011 +#define FE_VMOVUPD256mr 0x30000001890011 +#define FE_VMOVSSmr 0x30000001210011 +#define FE_VMOVSDmr 0x30000001110011 +#define FE_VMOVLPSrrm 0xc0000001010012 +#define FE_VMOVHLPSrrr 0xc0000001010012 +#define FE_VMOVLPDrrm 0xc0000001090012 +#define FE_VMOVDDUP128rm 0x38000001110012 +#define FE_VMOVDDUP128rr 0x38000001110012 +#define FE_VMOVDDUP256rm 0x38000001910012 +#define FE_VMOVDDUP256rr 0x38000001910012 +#define FE_VMOVSLDUP128rm 0x38000001210012 +#define FE_VMOVSLDUP128rr 0x38000001210012 +#define FE_VMOVSLDUP256rm 0x38000001a10012 +#define FE_VMOVSLDUP256rr 0x38000001a10012 +#define FE_VMOVLPSmr 0x30000001010013 +#define FE_VMOVLPDmr 0x30000001090013 +#define FE_VUNPCKLPS128rrr 0xc0000001010014 +#define FE_VUNPCKLPS128rrm 0xc0000001010014 +#define FE_VUNPCKLPS256rrr 0xc0000001810014 +#define FE_VUNPCKLPS256rrm 0xc0000001810014 +#define FE_VUNPCKLPD128rrr 0xc0000001090014 +#define FE_VUNPCKLPD128rrm 0xc0000001090014 +#define FE_VUNPCKLPD256rrr 0xc0000001890014 +#define FE_VUNPCKLPD256rrm 0xc0000001890014 +#define FE_VUNPCKHPS128rrr 0xc0000001010015 +#define FE_VUNPCKHPS128rrm 0xc0000001010015 +#define FE_VUNPCKHPS256rrr 0xc0000001810015 +#define FE_VUNPCKHPS256rrm 0xc0000001810015 +#define FE_VUNPCKHPD128rrr 0xc0000001090015 +#define FE_VUNPCKHPD128rrm 0xc0000001090015 +#define FE_VUNPCKHPD256rrr 0xc0000001890015 +#define FE_VUNPCKHPD256rrm 0xc0000001890015 +#define FE_VMOVHPSrrm 0xc0000001010016 +#define FE_VMOVLHPSrrr 0xc0000001010016 +#define FE_VMOVHPDrrm 0xc0000001090016 +#define FE_VMOVSHDUP128rm 0x38000001210016 +#define FE_VMOVSHDUP128rr 0x38000001210016 +#define FE_VMOVSHDUP256rm 0x38000001a10016 +#define FE_VMOVSHDUP256rr 0x38000001a10016 +#define FE_VMOVHPSmr 0x30000001010017 +#define FE_VMOVHPDmr 0x30000001090017 +#define FE_VMOVAPS128rm 0x38000001010028 +#define FE_VMOVAPS128rr 0x38000001010028 +#define FE_VMOVAPS256rm 0x38000001810028 +#define FE_VMOVAPS256rr 0x38000001810028 +#define FE_VMOVAPD128rm 0x38000001090028 +#define FE_VMOVAPD128rr 0x38000001090028 +#define FE_VMOVAPD256rm 0x38000001890028 +#define FE_VMOVAPD256rr 0x38000001890028 +#define FE_VMOVAPS128mr 0x30000001010029 +#define FE_VMOVAPS256mr 0x30000001810029 +#define FE_VMOVAPD128mr 0x30000001090029 +#define FE_VMOVAPD256mr 0x30000001890029 +#define FE_VCVTSI2SS32rrr 0xc000000121002a +#define FE_VCVTSI2SS32rrm 0xc000000121002a +#define FE_VCVTSI2SS64rrr 0xc000000161002a +#define FE_VCVTSI2SS64rrm 0xc000000161002a +#define FE_VCVTSI2SD32rrr 0xc000000111002a +#define FE_VCVTSI2SD32rrm 0xc000000111002a +#define FE_VCVTSI2SD64rrr 0xc000000151002a +#define FE_VCVTSI2SD64rrm 0xc000000151002a +#define FE_VMOVNTPS128mr 0x3000000101002b +#define FE_VMOVNTPS256mr 0x3000000181002b +#define FE_VMOVNTPD128mr 0x3000000109002b +#define FE_VMOVNTPD256mr 0x3000000189002b +#define FE_VCVTTSS2SI32rm 0x3800000121002c +#define FE_VCVTTSS2SI32rr 0x3800000121002c +#define FE_VCVTTSS2SI64rm 0x3800000161002c +#define FE_VCVTTSS2SI64rr 0x3800000161002c +#define FE_VCVTTSD2SI32rm 0x3800000111002c +#define FE_VCVTTSD2SI32rr 0x3800000111002c +#define FE_VCVTTSD2SI64rm 0x3800000151002c +#define FE_VCVTTSD2SI64rr 0x3800000151002c +#define FE_VCVTSS2SI32rm 0x3800000121002d +#define FE_VCVTSS2SI32rr 0x3800000121002d +#define FE_VCVTSS2SI64rm 0x3800000161002d +#define FE_VCVTSS2SI64rr 0x3800000161002d +#define FE_VCVTSD2SI32rm 0x3800000111002d +#define FE_VCVTSD2SI32rr 0x3800000111002d +#define FE_VCVTSD2SI64rm 0x3800000151002d +#define FE_VCVTSD2SI64rr 0x3800000151002d +#define FE_VUCOMISSrm 0x3800000101002e +#define FE_VUCOMISSrr 0x3800000101002e +#define FE_VUCOMISDrm 0x3800000109002e +#define FE_VUCOMISDrr 0x3800000109002e +#define FE_VCOMISSrm 0x3800000101002f +#define FE_VCOMISSrr 0x3800000101002f +#define FE_VCOMISDrm 0x3800000109002f +#define FE_VCOMISDrr 0x3800000109002f +#define FE_VMOVMSKPS128rr 0x38000001010050 +#define FE_VMOVMSKPS256rr 0x38000001810050 +#define FE_VMOVMSKPD128rr 0x38000001090050 +#define FE_VMOVMSKPD256rr 0x38000001890050 +#define FE_VSQRTPS128rm 0x38000001010051 +#define FE_VSQRTPS128rr 0x38000001010051 +#define FE_VSQRTPS256rm 0x38000001810051 +#define FE_VSQRTPS256rr 0x38000001810051 +#define FE_VSQRTPD128rm 0x38000001090051 +#define FE_VSQRTPD128rr 0x38000001090051 +#define FE_VSQRTPD256rm 0x38000001890051 +#define FE_VSQRTPD256rr 0x38000001890051 +#define FE_VSQRTSSrrr 0xc0000001210051 +#define FE_VSQRTSSrrm 0xc0000001210051 +#define FE_VSQRTSDrrr 0xc0000001110051 +#define FE_VSQRTSDrrm 0xc0000001110051 +#define FE_VRSQRTPS128rm 0x38000001010052 +#define FE_VRSQRTPS128rr 0x38000001010052 +#define FE_VRSQRTPS256rm 0x38000001810052 +#define FE_VRSQRTPS256rr 0x38000001810052 +#define FE_VRSQRTSSrrr 0xc0000001210052 +#define FE_VRSQRTSSrrm 0xc0000001210052 +#define FE_VRCPPS128rm 0x38000001010053 +#define FE_VRCPPS128rr 0x38000001010053 +#define FE_VRCPPS256rm 0x38000001810053 +#define FE_VRCPPS256rr 0x38000001810053 +#define FE_VRCPSSrrr 0xc0000001210053 +#define FE_VRCPSSrrm 0xc0000001210053 +#define FE_VANDPS128rrr 0xc0000001010054 +#define FE_VANDPS128rrm 0xc0000001010054 +#define FE_VANDPS256rrr 0xc0000001810054 +#define FE_VANDPS256rrm 0xc0000001810054 +#define FE_VANDPD128rrr 0xc0000001090054 +#define FE_VANDPD128rrm 0xc0000001090054 +#define FE_VANDPD256rrr 0xc0000001890054 +#define FE_VANDPD256rrm 0xc0000001890054 +#define FE_VANDNPS128rrr 0xc0000001010055 +#define FE_VANDNPS128rrm 0xc0000001010055 +#define FE_VANDNPS256rrr 0xc0000001810055 +#define FE_VANDNPS256rrm 0xc0000001810055 +#define FE_VANDNPD128rrr 0xc0000001090055 +#define FE_VANDNPD128rrm 0xc0000001090055 +#define FE_VANDNPD256rrr 0xc0000001890055 +#define FE_VANDNPD256rrm 0xc0000001890055 +#define FE_VORPS128rrr 0xc0000001010056 +#define FE_VORPS128rrm 0xc0000001010056 +#define FE_VORPS256rrr 0xc0000001810056 +#define FE_VORPS256rrm 0xc0000001810056 +#define FE_VORPD128rrr 0xc0000001090056 +#define FE_VORPD128rrm 0xc0000001090056 +#define FE_VORPD256rrr 0xc0000001890056 +#define FE_VORPD256rrm 0xc0000001890056 +#define FE_VXORPS128rrr 0xc0000001010057 +#define FE_VXORPS128rrm 0xc0000001010057 +#define FE_VXORPS256rrr 0xc0000001810057 +#define FE_VXORPS256rrm 0xc0000001810057 +#define FE_VXORPD128rrr 0xc0000001090057 +#define FE_VXORPD128rrm 0xc0000001090057 +#define FE_VXORPD256rrr 0xc0000001890057 +#define FE_VXORPD256rrm 0xc0000001890057 +#define FE_VADDPS128rrr 0xc0000001010058 +#define FE_VADDPS128rrm 0xc0000001010058 +#define FE_VADDPS256rrr 0xc0000001810058 +#define FE_VADDPS256rrm 0xc0000001810058 +#define FE_VADDPD128rrr 0xc0000001090058 +#define FE_VADDPD128rrm 0xc0000001090058 +#define FE_VADDPD256rrr 0xc0000001890058 +#define FE_VADDPD256rrm 0xc0000001890058 +#define FE_VADDSSrrr 0xc0000001210058 +#define FE_VADDSSrrm 0xc0000001210058 +#define FE_VADDSDrrr 0xc0000001110058 +#define FE_VADDSDrrm 0xc0000001110058 +#define FE_VMULPS128rrr 0xc0000001010059 +#define FE_VMULPS128rrm 0xc0000001010059 +#define FE_VMULPS256rrr 0xc0000001810059 +#define FE_VMULPS256rrm 0xc0000001810059 +#define FE_VMULPD128rrr 0xc0000001090059 +#define FE_VMULPD128rrm 0xc0000001090059 +#define FE_VMULPD256rrr 0xc0000001890059 +#define FE_VMULPD256rrm 0xc0000001890059 +#define FE_VMULSSrrr 0xc0000001210059 +#define FE_VMULSSrrm 0xc0000001210059 +#define FE_VMULSDrrr 0xc0000001110059 +#define FE_VMULSDrrm 0xc0000001110059 +#define FE_VCVTPS2PD128rm 0x3800000101005a +#define FE_VCVTPS2PD128rr 0x3800000101005a +#define FE_VCVTPS2PD256rm 0x3800000181005a +#define FE_VCVTPS2PD256rr 0x3800000181005a +#define FE_VCVTPD2PS128rm 0x3800000109005a +#define FE_VCVTPD2PS128rr 0x3800000109005a +#define FE_VCVTPD2PS256rm 0x3800000189005a +#define FE_VCVTPD2PS256rr 0x3800000189005a +#define FE_VCVTSS2SDrrr 0xc000000121005a +#define FE_VCVTSS2SDrrm 0xc000000121005a +#define FE_VCVTSD2SSrrr 0xc000000111005a +#define FE_VCVTSD2SSrrm 0xc000000111005a +#define FE_VCVTDQ2PS128rm 0x3800000101005b +#define FE_VCVTDQ2PS128rr 0x3800000101005b +#define FE_VCVTDQ2PS256rm 0x3800000181005b +#define FE_VCVTDQ2PS256rr 0x3800000181005b +#define FE_VCVTPS2DQ128rm 0x3800000109005b +#define FE_VCVTPS2DQ128rr 0x3800000109005b +#define FE_VCVTPS2DQ256rm 0x3800000189005b +#define FE_VCVTPS2DQ256rr 0x3800000189005b +#define FE_VCVTTPS2DQ128rm 0x3800000121005b +#define FE_VCVTTPS2DQ128rr 0x3800000121005b +#define FE_VCVTTPS2DQ256rm 0x38000001a1005b +#define FE_VCVTTPS2DQ256rr 0x38000001a1005b +#define FE_VSUBPS128rrr 0xc000000101005c +#define FE_VSUBPS128rrm 0xc000000101005c +#define FE_VSUBPS256rrr 0xc000000181005c +#define FE_VSUBPS256rrm 0xc000000181005c +#define FE_VSUBPD128rrr 0xc000000109005c +#define FE_VSUBPD128rrm 0xc000000109005c +#define FE_VSUBPD256rrr 0xc000000189005c +#define FE_VSUBPD256rrm 0xc000000189005c +#define FE_VSUBSSrrr 0xc000000121005c +#define FE_VSUBSSrrm 0xc000000121005c +#define FE_VSUBSDrrr 0xc000000111005c +#define FE_VSUBSDrrm 0xc000000111005c +#define FE_VMINPS128rrr 0xc000000101005d +#define FE_VMINPS128rrm 0xc000000101005d +#define FE_VMINPS256rrr 0xc000000181005d +#define FE_VMINPS256rrm 0xc000000181005d +#define FE_VMINPD128rrr 0xc000000109005d +#define FE_VMINPD128rrm 0xc000000109005d +#define FE_VMINPD256rrr 0xc000000189005d +#define FE_VMINPD256rrm 0xc000000189005d +#define FE_VMINSSrrr 0xc000000121005d +#define FE_VMINSSrrm 0xc000000121005d +#define FE_VMINSDrrr 0xc000000111005d +#define FE_VMINSDrrm 0xc000000111005d +#define FE_VDIVPS128rrr 0xc000000101005e +#define FE_VDIVPS128rrm 0xc000000101005e +#define FE_VDIVPS256rrr 0xc000000181005e +#define FE_VDIVPS256rrm 0xc000000181005e +#define FE_VDIVPD128rrr 0xc000000109005e +#define FE_VDIVPD128rrm 0xc000000109005e +#define FE_VDIVPD256rrr 0xc000000189005e +#define FE_VDIVPD256rrm 0xc000000189005e +#define FE_VDIVSSrrr 0xc000000121005e +#define FE_VDIVSSrrm 0xc000000121005e +#define FE_VDIVSDrrr 0xc000000111005e +#define FE_VDIVSDrrm 0xc000000111005e +#define FE_VMAXPS128rrr 0xc000000101005f +#define FE_VMAXPS128rrm 0xc000000101005f +#define FE_VMAXPS256rrr 0xc000000181005f +#define FE_VMAXPS256rrm 0xc000000181005f +#define FE_VMAXPD128rrr 0xc000000109005f +#define FE_VMAXPD128rrm 0xc000000109005f +#define FE_VMAXPD256rrr 0xc000000189005f +#define FE_VMAXPD256rrm 0xc000000189005f +#define FE_VMAXSSrrr 0xc000000121005f +#define FE_VMAXSSrrm 0xc000000121005f +#define FE_VMAXSDrrr 0xc000000111005f +#define FE_VMAXSDrrm 0xc000000111005f +#define FE_VPUNPCKLBW128rrr 0xc0000001090060 +#define FE_VPUNPCKLBW128rrm 0xc0000001090060 +#define FE_VPUNPCKLBW256rrr 0xc0000001890060 +#define FE_VPUNPCKLBW256rrm 0xc0000001890060 +#define FE_VPUNPCKLWD128rrr 0xc0000001090061 +#define FE_VPUNPCKLWD128rrm 0xc0000001090061 +#define FE_VPUNPCKLWD256rrr 0xc0000001890061 +#define FE_VPUNPCKLWD256rrm 0xc0000001890061 +#define FE_VPUNPCKLDQ128rrr 0xc0000001090062 +#define FE_VPUNPCKLDQ128rrm 0xc0000001090062 +#define FE_VPUNPCKLDQ256rrr 0xc0000001890062 +#define FE_VPUNPCKLDQ256rrm 0xc0000001890062 +#define FE_VPACKSSWB128rrr 0xc0000001090063 +#define FE_VPACKSSWB128rrm 0xc0000001090063 +#define FE_VPACKSSWB256rrr 0xc0000001890063 +#define FE_VPACKSSWB256rrm 0xc0000001890063 +#define FE_VPCMPGTB128rrr 0xc0000001090064 +#define FE_VPCMPGTB128rrm 0xc0000001090064 +#define FE_VPCMPGTB256rrr 0xc0000001890064 +#define FE_VPCMPGTB256rrm 0xc0000001890064 +#define FE_VPCMPGTW128rrr 0xc0000001090065 +#define FE_VPCMPGTW128rrm 0xc0000001090065 +#define FE_VPCMPGTW256rrr 0xc0000001890065 +#define FE_VPCMPGTW256rrm 0xc0000001890065 +#define FE_VPCMPGTD128rrr 0xc0000001090066 +#define FE_VPCMPGTD128rrm 0xc0000001090066 +#define FE_VPCMPGTD256rrr 0xc0000001890066 +#define FE_VPCMPGTD256rrm 0xc0000001890066 +#define FE_VPACKUSWB128rrr 0xc0000001090067 +#define FE_VPACKUSWB128rrm 0xc0000001090067 +#define FE_VPACKUSWB256rrr 0xc0000001890067 +#define FE_VPACKUSWB256rrm 0xc0000001890067 +#define FE_VPUNPCKHBW128rrr 0xc0000001090068 +#define FE_VPUNPCKHBW128rrm 0xc0000001090068 +#define FE_VPUNPCKHBW256rrr 0xc0000001890068 +#define FE_VPUNPCKHBW256rrm 0xc0000001890068 +#define FE_VPUNPCKHWD128rrr 0xc0000001090069 +#define FE_VPUNPCKHWD128rrm 0xc0000001090069 +#define FE_VPUNPCKHWD256rrr 0xc0000001890069 +#define FE_VPUNPCKHWD256rrm 0xc0000001890069 +#define FE_VPUNPCKHDQ128rrr 0xc000000109006a +#define FE_VPUNPCKHDQ128rrm 0xc000000109006a +#define FE_VPUNPCKHDQ256rrr 0xc000000189006a +#define FE_VPUNPCKHDQ256rrm 0xc000000189006a +#define FE_VPACKSSDW128rrr 0xc000000109006b +#define FE_VPACKSSDW128rrm 0xc000000109006b +#define FE_VPACKSSDW256rrr 0xc000000189006b +#define FE_VPACKSSDW256rrm 0xc000000189006b +#define FE_VPUNPCKLQDQ128rrr 0xc000000109006c +#define FE_VPUNPCKLQDQ128rrm 0xc000000109006c +#define FE_VPUNPCKLQDQ256rrr 0xc000000189006c +#define FE_VPUNPCKLQDQ256rrm 0xc000000189006c +#define FE_VPUNPCKHQDQ128rrr 0xc000000109006d +#define FE_VPUNPCKHQDQ128rrm 0xc000000109006d +#define FE_VPUNPCKHQDQ256rrr 0xc000000189006d +#define FE_VPUNPCKHQDQ256rrm 0xc000000189006d +#define FE_VMOVD_G2Xrm 0x3800000109006e +#define FE_VMOVD_G2Xrr 0x3800000109006e +#define FE_VMOVQ_G2Xrm 0x3800000149006e +#define FE_VMOVQ_G2Xrr 0x3800000149006e +#define FE_VMOVDQA128rm 0x3800000109006f +#define FE_VMOVDQA128rr 0x3800000109006f +#define FE_VMOVDQA256rm 0x3800000189006f +#define FE_VMOVDQA256rr 0x3800000189006f +#define FE_VMOVDQU128rm 0x3800000121006f +#define FE_VMOVDQU128rr 0x3800000121006f +#define FE_VMOVDQU256rm 0x38000001a1006f +#define FE_VMOVDQU256rr 0x38000001a1006f +#define FE_VPSHUFD128rmi 0x50800001090070 +#define FE_VPSHUFD128rri 0x50800001090070 +#define FE_VPSHUFD256rmi 0x50800001890070 +#define FE_VPSHUFD256rri 0x50800001890070 +#define FE_VPSHUFHW128rmi 0x50800001210070 +#define FE_VPSHUFHW128rri 0x50800001210070 +#define FE_VPSHUFHW256rmi 0x50800001a10070 +#define FE_VPSHUFHW256rri 0x50800001a10070 +#define FE_VPSHUFLW128rmi 0x50800001110070 +#define FE_VPSHUFLW128rri 0x50800001110070 +#define FE_VPSHUFLW256rmi 0x50800001910070 +#define FE_VPSHUFLW256rri 0x50800001910070 +#define FE_VPSRLW128rri 0xe8800001090271 +#define FE_VPSRLW256rri 0xe8800001890271 +#define FE_VPSRAW128rri 0xe8800001090471 +#define FE_VPSRAW256rri 0xe8800001890471 +#define FE_VPSLLW128rri 0xe8800001090671 +#define FE_VPSLLW256rri 0xe8800001890671 +#define FE_VPSRLD128rri 0xe8800001090272 +#define FE_VPSRLD256rri 0xe8800001890272 +#define FE_VPSRAD128rri 0xe8800001090472 +#define FE_VPSRAD256rri 0xe8800001890472 +#define FE_VPSLLD128rri 0xe8800001090672 +#define FE_VPSLLD256rri 0xe8800001890672 +#define FE_VPSRLQ128rri 0xe8800001090273 +#define FE_VPSRLQ256rri 0xe8800001890273 +#define FE_VPSRLDQ128rri 0xe8800001090373 +#define FE_VPSRLDQ256rri 0xe8800001890373 +#define FE_VPSLLQ128rri 0xe8800001090673 +#define FE_VPSLLQ256rri 0xe8800001890673 +#define FE_VPSLLDQ128rri 0xe8800001090773 +#define FE_VPSLLDQ256rri 0xe8800001890773 +#define FE_VPCMPEQB128rrr 0xc0000001090074 +#define FE_VPCMPEQB128rrm 0xc0000001090074 +#define FE_VPCMPEQB256rrr 0xc0000001890074 +#define FE_VPCMPEQB256rrm 0xc0000001890074 +#define FE_VPCMPEQW128rrr 0xc0000001090075 +#define FE_VPCMPEQW128rrm 0xc0000001090075 +#define FE_VPCMPEQW256rrr 0xc0000001890075 +#define FE_VPCMPEQW256rrm 0xc0000001890075 +#define FE_VPCMPEQD128rrr 0xc0000001090076 +#define FE_VPCMPEQD128rrm 0xc0000001090076 +#define FE_VPCMPEQD256rrr 0xc0000001890076 +#define FE_VPCMPEQD256rrm 0xc0000001890076 +#define FE_VZEROUPPER 0x8000001010077 +#define FE_VZEROALL 0x8000001810077 +#define FE_VHADDPD128rrr 0xc000000109007c +#define FE_VHADDPD128rrm 0xc000000109007c +#define FE_VHADDPD256rrr 0xc000000189007c +#define FE_VHADDPD256rrm 0xc000000189007c +#define FE_VHADDPS128rrr 0xc000000111007c +#define FE_VHADDPS128rrm 0xc000000111007c +#define FE_VHADDPS256rrr 0xc000000191007c +#define FE_VHADDPS256rrm 0xc000000191007c +#define FE_VHSUBPD128rrr 0xc000000109007d +#define FE_VHSUBPD128rrm 0xc000000109007d +#define FE_VHSUBPD256rrr 0xc000000189007d +#define FE_VHSUBPD256rrm 0xc000000189007d +#define FE_VHSUBPS128rrr 0xc000000111007d +#define FE_VHSUBPS128rrm 0xc000000111007d +#define FE_VHSUBPS256rrr 0xc000000191007d +#define FE_VHSUBPS256rrm 0xc000000191007d +#define FE_VMOVD_X2Gmr 0x3000000109007e +#define FE_VMOVD_X2Grr 0x3000000109007e +#define FE_VMOVQ_X2Gmr 0x3000000149007e +#define FE_VMOVQ_X2Grr 0x3000000149007e +#define FE_VMOVQrm 0x3800000121007e +#define FE_VMOVQrr 0x3800000121007e +#define FE_VMOVDQA128mr 0x3000000109007f +#define FE_VMOVDQA256mr 0x3000000189007f +#define FE_VMOVDQU128mr 0x3000000121007f +#define FE_VMOVDQU256mr 0x30000001a1007f +#define FE_VLDMXCSRm 0x100000010102ae +#define FE_VSTMXCSRm 0x100000010103ae +#define FE_VCMPPS128rrmi 0xc88000010100c2 +#define FE_VCMPPS128rrri 0xc88000010100c2 +#define FE_VCMPPS256rrmi 0xc88000018100c2 +#define FE_VCMPPS256rrri 0xc88000018100c2 +#define FE_VCMPPD128rrmi 0xc88000010900c2 +#define FE_VCMPPD128rrri 0xc88000010900c2 +#define FE_VCMPPD256rrmi 0xc88000018900c2 +#define FE_VCMPPD256rrri 0xc88000018900c2 +#define FE_VCMPSSrrmi 0xc88000012100c2 +#define FE_VCMPSSrrri 0xc88000012100c2 +#define FE_VCMPSDrrmi 0xc88000011100c2 +#define FE_VCMPSDrrri 0xc88000011100c2 +#define FE_VPINSRWrrmi 0xc88000010900c4 +#define FE_VPINSRWrrri 0xc88000010900c4 +#define FE_VPEXTRWrri 0x508000010900c5 +#define FE_VSHUFPS128rrmi 0xc88000010100c6 +#define FE_VSHUFPS128rrri 0xc88000010100c6 +#define FE_VSHUFPS256rrmi 0xc88000018100c6 +#define FE_VSHUFPS256rrri 0xc88000018100c6 +#define FE_VSHUFPD128rrmi 0xc88000010900c6 +#define FE_VSHUFPD128rrri 0xc88000010900c6 +#define FE_VSHUFPD256rrmi 0xc88000018900c6 +#define FE_VSHUFPD256rrri 0xc88000018900c6 +#define FE_VADDSUBPD128rrr 0xc00000010900d0 +#define FE_VADDSUBPD128rrm 0xc00000010900d0 +#define FE_VADDSUBPD256rrr 0xc00000018900d0 +#define FE_VADDSUBPD256rrm 0xc00000018900d0 +#define FE_VADDSUBPS128rrr 0xc00000011100d0 +#define FE_VADDSUBPS128rrm 0xc00000011100d0 +#define FE_VADDSUBPS256rrr 0xc00000019100d0 +#define FE_VADDSUBPS256rrm 0xc00000019100d0 +#define FE_VPSRLW128rrr 0xc00000010900d1 +#define FE_VPSRLW128rrm 0xc00000010900d1 +#define FE_VPSRLW256rrr 0xc00000018900d1 +#define FE_VPSRLW256rrm 0xc00000018900d1 +#define FE_VPSRLD128rrr 0xc00000010900d2 +#define FE_VPSRLD128rrm 0xc00000010900d2 +#define FE_VPSRLD256rrr 0xc00000018900d2 +#define FE_VPSRLD256rrm 0xc00000018900d2 +#define FE_VPSRLQ128rrr 0xc00000010900d3 +#define FE_VPSRLQ128rrm 0xc00000010900d3 +#define FE_VPSRLQ256rrr 0xc00000018900d3 +#define FE_VPSRLQ256rrm 0xc00000018900d3 +#define FE_VPADDQ128rrr 0xc00000010900d4 +#define FE_VPADDQ128rrm 0xc00000010900d4 +#define FE_VPADDQ256rrr 0xc00000018900d4 +#define FE_VPADDQ256rrm 0xc00000018900d4 +#define FE_VPMULLW128rrr 0xc00000010900d5 +#define FE_VPMULLW128rrm 0xc00000010900d5 +#define FE_VPMULLW256rrr 0xc00000018900d5 +#define FE_VPMULLW256rrm 0xc00000018900d5 +#define FE_VMOVQmr 0x300000010900d6 +#define FE_VPMOVMSKB128rr 0x380000010900d7 +#define FE_VPMOVMSKB256rr 0x380000018900d7 +#define FE_VPSUBUSB128rrr 0xc00000010900d8 +#define FE_VPSUBUSB128rrm 0xc00000010900d8 +#define FE_VPSUBUSB256rrr 0xc00000018900d8 +#define FE_VPSUBUSB256rrm 0xc00000018900d8 +#define FE_VPSUBUSW128rrr 0xc00000010900d9 +#define FE_VPSUBUSW128rrm 0xc00000010900d9 +#define FE_VPSUBUSW256rrr 0xc00000018900d9 +#define FE_VPSUBUSW256rrm 0xc00000018900d9 +#define FE_VPMINUB128rrr 0xc00000010900da +#define FE_VPMINUB128rrm 0xc00000010900da +#define FE_VPMINUB256rrr 0xc00000018900da +#define FE_VPMINUB256rrm 0xc00000018900da +#define FE_VPAND128rrr 0xc00000010900db +#define FE_VPAND128rrm 0xc00000010900db +#define FE_VPAND256rrr 0xc00000018900db +#define FE_VPAND256rrm 0xc00000018900db +#define FE_VPADDUSB128rrr 0xc00000010900dc +#define FE_VPADDUSB128rrm 0xc00000010900dc +#define FE_VPADDUSB256rrr 0xc00000018900dc +#define FE_VPADDUSB256rrm 0xc00000018900dc +#define FE_VPADDUSW128rrr 0xc00000010900dd +#define FE_VPADDUSW128rrm 0xc00000010900dd +#define FE_VPADDUSW256rrr 0xc00000018900dd +#define FE_VPADDUSW256rrm 0xc00000018900dd +#define FE_VPMAXUB128rrr 0xc00000010900de +#define FE_VPMAXUB128rrm 0xc00000010900de +#define FE_VPMAXUB256rrr 0xc00000018900de +#define FE_VPMAXUB256rrm 0xc00000018900de +#define FE_VPANDN128rrr 0xc00000010900df +#define FE_VPANDN128rrm 0xc00000010900df +#define FE_VPANDN256rrr 0xc00000018900df +#define FE_VPANDN256rrm 0xc00000018900df +#define FE_VPAVGB128rrr 0xc00000010900e0 +#define FE_VPAVGB128rrm 0xc00000010900e0 +#define FE_VPAVGB256rrr 0xc00000018900e0 +#define FE_VPAVGB256rrm 0xc00000018900e0 +#define FE_VPSRAW128rrr 0xc00000010900e1 +#define FE_VPSRAW128rrm 0xc00000010900e1 +#define FE_VPSRAW256rrr 0xc00000018900e1 +#define FE_VPSRAW256rrm 0xc00000018900e1 +#define FE_VPSRAD128rrr 0xc00000010900e2 +#define FE_VPSRAD128rrm 0xc00000010900e2 +#define FE_VPSRAD256rrr 0xc00000018900e2 +#define FE_VPSRAD256rrm 0xc00000018900e2 +#define FE_VPAVGW128rrr 0xc00000010900e3 +#define FE_VPAVGW128rrm 0xc00000010900e3 +#define FE_VPAVGW256rrr 0xc00000018900e3 +#define FE_VPAVGW256rrm 0xc00000018900e3 +#define FE_VPMULHUW128rrr 0xc00000010900e4 +#define FE_VPMULHUW128rrm 0xc00000010900e4 +#define FE_VPMULHUW256rrr 0xc00000018900e4 +#define FE_VPMULHUW256rrm 0xc00000018900e4 +#define FE_VPMULHW128rrr 0xc00000010900e5 +#define FE_VPMULHW128rrm 0xc00000010900e5 +#define FE_VPMULHW256rrr 0xc00000018900e5 +#define FE_VPMULHW256rrm 0xc00000018900e5 +#define FE_VCVTTPD2DQ128rm 0x380000010900e6 +#define FE_VCVTTPD2DQ128rr 0x380000010900e6 +#define FE_VCVTTPD2DQ256rm 0x380000018900e6 +#define FE_VCVTTPD2DQ256rr 0x380000018900e6 +#define FE_VCVTDQ2PD128rm 0x380000012100e6 +#define FE_VCVTDQ2PD128rr 0x380000012100e6 +#define FE_VCVTDQ2PD256rm 0x38000001a100e6 +#define FE_VCVTDQ2PD256rr 0x38000001a100e6 +#define FE_VCVTPD2DQ128rm 0x380000011100e6 +#define FE_VCVTPD2DQ128rr 0x380000011100e6 +#define FE_VCVTPD2DQ256rm 0x380000019100e6 +#define FE_VCVTPD2DQ256rr 0x380000019100e6 +#define FE_VMOVNTDQ128mr 0x300000010900e7 +#define FE_VMOVNTDQ256mr 0x300000018900e7 +#define FE_VPSUBSB128rrr 0xc00000010900e8 +#define FE_VPSUBSB128rrm 0xc00000010900e8 +#define FE_VPSUBSB256rrr 0xc00000018900e8 +#define FE_VPSUBSB256rrm 0xc00000018900e8 +#define FE_VPSUBSW128rrr 0xc00000010900e9 +#define FE_VPSUBSW128rrm 0xc00000010900e9 +#define FE_VPSUBSW256rrr 0xc00000018900e9 +#define FE_VPSUBSW256rrm 0xc00000018900e9 +#define FE_VPOR128rrr 0xc00000010900eb +#define FE_VPOR128rrm 0xc00000010900eb +#define FE_VPOR256rrr 0xc00000018900eb +#define FE_VPOR256rrm 0xc00000018900eb +#define FE_VPADDSB128rrr 0xc00000010900ec +#define FE_VPADDSB128rrm 0xc00000010900ec +#define FE_VPADDSB256rrr 0xc00000018900ec +#define FE_VPADDSB256rrm 0xc00000018900ec +#define FE_VPMINSW128rrr 0xc00000010900ea +#define FE_VPMINSW128rrm 0xc00000010900ea +#define FE_VPMINSW256rrr 0xc00000018900ea +#define FE_VPMINSW256rrm 0xc00000018900ea +#define FE_VPADDSW128rrr 0xc00000010900ed +#define FE_VPADDSW128rrm 0xc00000010900ed +#define FE_VPADDSW256rrr 0xc00000018900ed +#define FE_VPADDSW256rrm 0xc00000018900ed +#define FE_VPMAXSW128rrr 0xc00000010900ee +#define FE_VPMAXSW128rrm 0xc00000010900ee +#define FE_VPMAXSW256rrr 0xc00000018900ee +#define FE_VPMAXSW256rrm 0xc00000018900ee +#define FE_VPXOR128rrr 0xc00000010900ef +#define FE_VPXOR128rrm 0xc00000010900ef +#define FE_VPXOR256rrr 0xc00000018900ef +#define FE_VPXOR256rrm 0xc00000018900ef +#define FE_VLDDQU128rm 0x380000011100f0 +#define FE_VLDDQU256rm 0x380000019100f0 +#define FE_VPSLLW128rrr 0xc00000010900f1 +#define FE_VPSLLW128rrm 0xc00000010900f1 +#define FE_VPSLLW256rrr 0xc00000018900f1 +#define FE_VPSLLW256rrm 0xc00000018900f1 +#define FE_VPSLLD128rrr 0xc00000010900f2 +#define FE_VPSLLD128rrm 0xc00000010900f2 +#define FE_VPSLLD256rrr 0xc00000018900f2 +#define FE_VPSLLD256rrm 0xc00000018900f2 +#define FE_VPSLLQ128rrr 0xc00000010900f3 +#define FE_VPSLLQ128rrm 0xc00000010900f3 +#define FE_VPSLLQ256rrr 0xc00000018900f3 +#define FE_VPSLLQ256rrm 0xc00000018900f3 +#define FE_VPMULUDQ128rrr 0xc00000010900f4 +#define FE_VPMULUDQ128rrm 0xc00000010900f4 +#define FE_VPMULUDQ256rrr 0xc00000018900f4 +#define FE_VPMULUDQ256rrm 0xc00000018900f4 +#define FE_VPMADDWD128rrr 0xc00000010900f5 +#define FE_VPMADDWD128rrm 0xc00000010900f5 +#define FE_VPMADDWD256rrr 0xc00000018900f5 +#define FE_VPMADDWD256rrm 0xc00000018900f5 +#define FE_VPSADBW128rrr 0xc00000010900f6 +#define FE_VPSADBW128rrm 0xc00000010900f6 +#define FE_VPSADBW256rrr 0xc00000018900f6 +#define FE_VPSADBW256rrm 0xc00000018900f6 +#define FE_VMASKMOVDQU128rr 0x380000010900f7 +#define FE_VPSUBB128rrr 0xc00000010900f8 +#define FE_VPSUBB128rrm 0xc00000010900f8 +#define FE_VPSUBB256rrr 0xc00000018900f8 +#define FE_VPSUBB256rrm 0xc00000018900f8 +#define FE_VPSUBW128rrr 0xc00000010900f9 +#define FE_VPSUBW128rrm 0xc00000010900f9 +#define FE_VPSUBW256rrr 0xc00000018900f9 +#define FE_VPSUBW256rrm 0xc00000018900f9 +#define FE_VPSUBD128rrr 0xc00000010900fa +#define FE_VPSUBD128rrm 0xc00000010900fa +#define FE_VPSUBD256rrr 0xc00000018900fa +#define FE_VPSUBD256rrm 0xc00000018900fa +#define FE_VPSUBQ128rrr 0xc00000010900fb +#define FE_VPSUBQ128rrm 0xc00000010900fb +#define FE_VPSUBQ256rrr 0xc00000018900fb +#define FE_VPSUBQ256rrm 0xc00000018900fb +#define FE_VPADDB128rrr 0xc00000010900fc +#define FE_VPADDB128rrm 0xc00000010900fc +#define FE_VPADDB256rrr 0xc00000018900fc +#define FE_VPADDB256rrm 0xc00000018900fc +#define FE_VPADDW128rrr 0xc00000010900fd +#define FE_VPADDW128rrm 0xc00000010900fd +#define FE_VPADDW256rrr 0xc00000018900fd +#define FE_VPADDW256rrm 0xc00000018900fd +#define FE_VPADDD128rrr 0xc00000010900fe +#define FE_VPADDD128rrm 0xc00000010900fe +#define FE_VPADDD256rrr 0xc00000018900fe +#define FE_VPADDD256rrm 0xc00000018900fe +#define FE_VPSHUFB128rrr 0xc00000010a0000 +#define FE_VPSHUFB128rrm 0xc00000010a0000 +#define FE_VPSHUFB256rrr 0xc00000018a0000 +#define FE_VPSHUFB256rrm 0xc00000018a0000 +#define FE_VPHADDW128rrr 0xc00000010a0001 +#define FE_VPHADDW128rrm 0xc00000010a0001 +#define FE_VPHADDW256rrr 0xc00000018a0001 +#define FE_VPHADDW256rrm 0xc00000018a0001 +#define FE_VPHADDD128rrr 0xc00000010a0002 +#define FE_VPHADDD128rrm 0xc00000010a0002 +#define FE_VPHADDD256rrr 0xc00000018a0002 +#define FE_VPHADDD256rrm 0xc00000018a0002 +#define FE_VPHADDSW128rrr 0xc00000010a0003 +#define FE_VPHADDSW128rrm 0xc00000010a0003 +#define FE_VPHADDSW256rrr 0xc00000018a0003 +#define FE_VPHADDSW256rrm 0xc00000018a0003 +#define FE_VPMADDUBSW128rrr 0xc00000010a0004 +#define FE_VPMADDUBSW128rrm 0xc00000010a0004 +#define FE_VPMADDUBSW256rrr 0xc00000018a0004 +#define FE_VPMADDUBSW256rrm 0xc00000018a0004 +#define FE_VPHSUBW128rrr 0xc00000010a0005 +#define FE_VPHSUBW128rrm 0xc00000010a0005 +#define FE_VPHSUBW256rrr 0xc00000018a0005 +#define FE_VPHSUBW256rrm 0xc00000018a0005 +#define FE_VPHSUBD128rrr 0xc00000010a0006 +#define FE_VPHSUBD128rrm 0xc00000010a0006 +#define FE_VPHSUBD256rrr 0xc00000018a0006 +#define FE_VPHSUBD256rrm 0xc00000018a0006 +#define FE_VPHSUBSW128rrr 0xc00000010a0007 +#define FE_VPHSUBSW128rrm 0xc00000010a0007 +#define FE_VPHSUBSW256rrr 0xc00000018a0007 +#define FE_VPHSUBSW256rrm 0xc00000018a0007 +#define FE_VPSIGNB128rrr 0xc00000010a0008 +#define FE_VPSIGNB128rrm 0xc00000010a0008 +#define FE_VPSIGNB256rrr 0xc00000018a0008 +#define FE_VPSIGNB256rrm 0xc00000018a0008 +#define FE_VPSIGNW128rrr 0xc00000010a0009 +#define FE_VPSIGNW128rrm 0xc00000010a0009 +#define FE_VPSIGNW256rrr 0xc00000018a0009 +#define FE_VPSIGNW256rrm 0xc00000018a0009 +#define FE_VPSIGND128rrr 0xc00000010a000a +#define FE_VPSIGND128rrm 0xc00000010a000a +#define FE_VPSIGND256rrr 0xc00000018a000a +#define FE_VPSIGND256rrm 0xc00000018a000a +#define FE_VPMULHRSW128rrr 0xc00000010a000b +#define FE_VPMULHRSW128rrm 0xc00000010a000b +#define FE_VPMULHRSW256rrr 0xc00000018a000b +#define FE_VPMULHRSW256rrm 0xc00000018a000b +#define FE_VPERMILPS128rrr 0xc00000010a000c +#define FE_VPERMILPS128rrm 0xc00000010a000c +#define FE_VPERMILPS256rrr 0xc00000018a000c +#define FE_VPERMILPS256rrm 0xc00000018a000c +#define FE_VPERMILPD128rrr 0xc00000010a000d +#define FE_VPERMILPD128rrm 0xc00000010a000d +#define FE_VPERMILPD256rrr 0xc00000018a000d +#define FE_VPERMILPD256rrm 0xc00000018a000d +#define FE_VTESTPS128rm 0x380000010a000e +#define FE_VTESTPS128rr 0x380000010a000e +#define FE_VTESTPS256rm 0x380000018a000e +#define FE_VTESTPS256rr 0x380000018a000e +#define FE_VTESTPD128rm 0x380000010a000f +#define FE_VTESTPD128rr 0x380000010a000f +#define FE_VTESTPD256rm 0x380000018a000f +#define FE_VTESTPD256rr 0x380000018a000f +#define FE_VCVTPH2PS128rm 0x380000010a0013 +#define FE_VCVTPH2PS128rr 0x380000010a0013 +#define FE_VCVTPH2PS256rm 0x380000018a0013 +#define FE_VCVTPH2PS256rr 0x380000018a0013 +#define FE_VPERMPS256rrr 0xc00000018a0016 +#define FE_VPERMPS256rrm 0xc00000018a0016 +#define FE_VPTEST128rm 0x380000010a0017 +#define FE_VPTEST128rr 0x380000010a0017 +#define FE_VPTEST256rm 0x380000018a0017 +#define FE_VPTEST256rr 0x380000018a0017 +#define FE_VBROADCASTSS128rm 0x380000010a0018 +#define FE_VBROADCASTSS128rr 0x380000010a0018 +#define FE_VBROADCASTSS256rm 0x380000018a0018 +#define FE_VBROADCASTSS256rr 0x380000018a0018 +#define FE_VBROADCASTSD256rm 0x380000018a0019 +#define FE_VBROADCASTSD256rr 0x380000018a0019 +#define FE_VBROADCASTF128_256rm 0x380000018a001a +#define FE_VBROADCASTF128_256rr 0x380000018a001a +#define FE_VPABSB128rm 0x380000010a001c +#define FE_VPABSB128rr 0x380000010a001c +#define FE_VPABSB256rm 0x380000018a001c +#define FE_VPABSB256rr 0x380000018a001c +#define FE_VPABSW128rm 0x380000010a001d +#define FE_VPABSW128rr 0x380000010a001d +#define FE_VPABSW256rm 0x380000018a001d +#define FE_VPABSW256rr 0x380000018a001d +#define FE_VPABSD128rm 0x380000010a001e +#define FE_VPABSD128rr 0x380000010a001e +#define FE_VPABSD256rm 0x380000018a001e +#define FE_VPABSD256rr 0x380000018a001e +#define FE_VPMOVSXBW128rm 0x380000010a0020 +#define FE_VPMOVSXBW128rr 0x380000010a0020 +#define FE_VPMOVSXBW256rm 0x380000018a0020 +#define FE_VPMOVSXBW256rr 0x380000018a0020 +#define FE_VPMOVSXBD128rm 0x380000010a0021 +#define FE_VPMOVSXBD128rr 0x380000010a0021 +#define FE_VPMOVSXBD256rm 0x380000018a0021 +#define FE_VPMOVSXBD256rr 0x380000018a0021 +#define FE_VPMOVSXBQ128rm 0x380000010a0022 +#define FE_VPMOVSXBQ128rr 0x380000010a0022 +#define FE_VPMOVSXBQ256rm 0x380000018a0022 +#define FE_VPMOVSXBQ256rr 0x380000018a0022 +#define FE_VPMOVSXWD128rm 0x380000010a0023 +#define FE_VPMOVSXWD128rr 0x380000010a0023 +#define FE_VPMOVSXWD256rm 0x380000018a0023 +#define FE_VPMOVSXWD256rr 0x380000018a0023 +#define FE_VPMOVSXWQ128rm 0x380000010a0024 +#define FE_VPMOVSXWQ128rr 0x380000010a0024 +#define FE_VPMOVSXWQ256rm 0x380000018a0024 +#define FE_VPMOVSXWQ256rr 0x380000018a0024 +#define FE_VPMOVSXDQ128rm 0x380000010a0025 +#define FE_VPMOVSXDQ128rr 0x380000010a0025 +#define FE_VPMOVSXDQ256rm 0x380000018a0025 +#define FE_VPMOVSXDQ256rr 0x380000018a0025 +#define FE_VPMULDQ128rrr 0xc00000010a0028 +#define FE_VPMULDQ128rrm 0xc00000010a0028 +#define FE_VPMULDQ256rrr 0xc00000018a0028 +#define FE_VPMULDQ256rrm 0xc00000018a0028 +#define FE_VPCMPEQQ128rrr 0xc00000010a0029 +#define FE_VPCMPEQQ128rrm 0xc00000010a0029 +#define FE_VPCMPEQQ256rrr 0xc00000018a0029 +#define FE_VPCMPEQQ256rrm 0xc00000018a0029 +#define FE_VMOVNTDQA128rm 0x380000010a002a +#define FE_VMOVNTDQA256rm 0x380000018a002a +#define FE_VPACKUSDW128rrr 0xc00000010a002b +#define FE_VPACKUSDW128rrm 0xc00000010a002b +#define FE_VPACKUSDW256rrr 0xc00000018a002b +#define FE_VPACKUSDW256rrm 0xc00000018a002b +#define FE_VMASKMOVPS128rrm 0xc00000010a002c +#define FE_VMASKMOVPS256rrm 0xc00000018a002c +#define FE_VMASKMOVPD128rrm 0xc00000010a002d +#define FE_VMASKMOVPD256rrm 0xc00000018a002d +#define FE_VMASKMOVPS128mrr 0xf00000010a002e +#define FE_VMASKMOVPS256mrr 0xf00000018a002e +#define FE_VMASKMOVPD128mrr 0xf00000010a002f +#define FE_VMASKMOVPD256mrr 0xf00000018a002f +#define FE_VPMOVZXBW128rm 0x380000010a0030 +#define FE_VPMOVZXBW128rr 0x380000010a0030 +#define FE_VPMOVZXBW256rm 0x380000018a0030 +#define FE_VPMOVZXBW256rr 0x380000018a0030 +#define FE_VPMOVZXBD128rm 0x380000010a0031 +#define FE_VPMOVZXBD128rr 0x380000010a0031 +#define FE_VPMOVZXBD256rm 0x380000018a0031 +#define FE_VPMOVZXBD256rr 0x380000018a0031 +#define FE_VPMOVZXBQ128rm 0x380000010a0032 +#define FE_VPMOVZXBQ128rr 0x380000010a0032 +#define FE_VPMOVZXBQ256rm 0x380000018a0032 +#define FE_VPMOVZXBQ256rr 0x380000018a0032 +#define FE_VPMOVZXWD128rm 0x380000010a0033 +#define FE_VPMOVZXWD128rr 0x380000010a0033 +#define FE_VPMOVZXWD256rm 0x380000018a0033 +#define FE_VPMOVZXWD256rr 0x380000018a0033 +#define FE_VPMOVZXWQ128rm 0x380000010a0034 +#define FE_VPMOVZXWQ128rr 0x380000010a0034 +#define FE_VPMOVZXWQ256rm 0x380000018a0034 +#define FE_VPMOVZXWQ256rr 0x380000018a0034 +#define FE_VPMOVZXDQ128rm 0x380000010a0035 +#define FE_VPMOVZXDQ128rr 0x380000010a0035 +#define FE_VPMOVZXDQ256rm 0x380000018a0035 +#define FE_VPMOVZXDQ256rr 0x380000018a0035 +#define FE_VPERMD256rrr 0xc00000018a0036 +#define FE_VPERMD256rrm 0xc00000018a0036 +#define FE_VPCMPGTQ128rrr 0xc00000010a0037 +#define FE_VPCMPGTQ128rrm 0xc00000010a0037 +#define FE_VPCMPGTQ256rrr 0xc00000018a0037 +#define FE_VPCMPGTQ256rrm 0xc00000018a0037 +#define FE_VPMINSB128rrr 0xc00000010a0038 +#define FE_VPMINSB128rrm 0xc00000010a0038 +#define FE_VPMINSB256rrr 0xc00000018a0038 +#define FE_VPMINSB256rrm 0xc00000018a0038 +#define FE_VPMINSD128rrr 0xc00000010a0039 +#define FE_VPMINSD128rrm 0xc00000010a0039 +#define FE_VPMINSD256rrr 0xc00000018a0039 +#define FE_VPMINSD256rrm 0xc00000018a0039 +#define FE_VPMINUW128rrr 0xc00000010a003a +#define FE_VPMINUW128rrm 0xc00000010a003a +#define FE_VPMINUW256rrr 0xc00000018a003a +#define FE_VPMINUW256rrm 0xc00000018a003a +#define FE_VPMINUD128rrr 0xc00000010a003b +#define FE_VPMINUD128rrm 0xc00000010a003b +#define FE_VPMINUD256rrr 0xc00000018a003b +#define FE_VPMINUD256rrm 0xc00000018a003b +#define FE_VPMAXSB128rrr 0xc00000010a003c +#define FE_VPMAXSB128rrm 0xc00000010a003c +#define FE_VPMAXSB256rrr 0xc00000018a003c +#define FE_VPMAXSB256rrm 0xc00000018a003c +#define FE_VPMAXSD128rrr 0xc00000010a003d +#define FE_VPMAXSD128rrm 0xc00000010a003d +#define FE_VPMAXSD256rrr 0xc00000018a003d +#define FE_VPMAXSD256rrm 0xc00000018a003d +#define FE_VPMAXUW128rrr 0xc00000010a003e +#define FE_VPMAXUW128rrm 0xc00000010a003e +#define FE_VPMAXUW256rrr 0xc00000018a003e +#define FE_VPMAXUW256rrm 0xc00000018a003e +#define FE_VPMAXUD128rrr 0xc00000010a003f +#define FE_VPMAXUD128rrm 0xc00000010a003f +#define FE_VPMAXUD256rrr 0xc00000018a003f +#define FE_VPMAXUD256rrm 0xc00000018a003f +#define FE_VPMULLD128rrr 0xc00000010a0040 +#define FE_VPMULLD128rrm 0xc00000010a0040 +#define FE_VPMULLD256rrr 0xc00000018a0040 +#define FE_VPMULLD256rrm 0xc00000018a0040 +#define FE_VPHMINPOSUW128rm 0x380000010a0041 +#define FE_VPHMINPOSUW128rr 0x380000010a0041 +#define FE_VPSRLVD128rrr 0xc00000010a0045 +#define FE_VPSRLVD128rrm 0xc00000010a0045 +#define FE_VPSRLVD256rrr 0xc00000018a0045 +#define FE_VPSRLVD256rrm 0xc00000018a0045 +#define FE_VPSRLVQ128rrr 0xc00000014a0045 +#define FE_VPSRLVQ128rrm 0xc00000014a0045 +#define FE_VPSRLVQ256rrr 0xc0000001ca0045 +#define FE_VPSRLVQ256rrm 0xc0000001ca0045 +#define FE_VPSRAVD128rrr 0xc00000010a0046 +#define FE_VPSRAVD128rrm 0xc00000010a0046 +#define FE_VPSRAVD256rrr 0xc00000018a0046 +#define FE_VPSRAVD256rrm 0xc00000018a0046 +#define FE_VPSLLVD128rrr 0xc00000010a0047 +#define FE_VPSLLVD128rrm 0xc00000010a0047 +#define FE_VPSLLVD256rrr 0xc00000018a0047 +#define FE_VPSLLVD256rrm 0xc00000018a0047 +#define FE_VPSLLVQ128rrr 0xc00000014a0047 +#define FE_VPSLLVQ128rrm 0xc00000014a0047 +#define FE_VPSLLVQ256rrr 0xc0000001ca0047 +#define FE_VPSLLVQ256rrm 0xc0000001ca0047 +#define FE_VPBROADCASTD128rm 0x380000010a0058 +#define FE_VPBROADCASTD128rr 0x380000010a0058 +#define FE_VPBROADCASTD256rm 0x380000018a0058 +#define FE_VPBROADCASTD256rr 0x380000018a0058 +#define FE_VPBROADCASTQ128rm 0x380000010a0059 +#define FE_VPBROADCASTQ128rr 0x380000010a0059 +#define FE_VPBROADCASTQ256rm 0x380000018a0059 +#define FE_VPBROADCASTQ256rr 0x380000018a0059 +#define FE_VBROADCASTI128rm 0x380000018a005a +#define FE_VPBROADCASTB128rm 0x380000010a0078 +#define FE_VPBROADCASTB128rr 0x380000010a0078 +#define FE_VPBROADCASTB256rm 0x380000018a0078 +#define FE_VPBROADCASTB256rr 0x380000018a0078 +#define FE_VPBROADCASTW128rm 0x380000010a0079 +#define FE_VPBROADCASTW128rr 0x380000010a0079 +#define FE_VPBROADCASTW256rm 0x380000018a0079 +#define FE_VPBROADCASTW256rr 0x380000018a0079 +#define FE_VPMASKMOVD128rrm 0xc00000010a008c +#define FE_VPMASKMOVD256rrm 0xc00000018a008c +#define FE_VPMASKMOVQ128rrm 0xc00000014a008c +#define FE_VPMASKMOVQ256rrm 0xc0000001ca008c +#define FE_VPMASKMOVD128mrr 0xf00000010a008e +#define FE_VPMASKMOVD256mrr 0xf00000018a008e +#define FE_VPMASKMOVQ128mrr 0xf00000014a008e +#define FE_VPMASKMOVQ256mrr 0xf0000001ca008e +#define FE_VPGATHERDD128rmr 0xd80000090a0090 +#define FE_VPGATHERDD256rmr 0xd80000098a0090 +#define FE_VPGATHERDQ128rmr 0xd80000094a0090 +#define FE_VPGATHERDQ256rmr 0xd8000009ca0090 +#define FE_VPGATHERQD128rmr 0xd80000090a0091 +#define FE_VPGATHERQD256rmr 0xd80000098a0091 +#define FE_VPGATHERQQ128rmr 0xd80000094a0091 +#define FE_VPGATHERQQ256rmr 0xd8000009ca0091 +#define FE_VGATHERDPS128rmr 0xd80000090a0092 +#define FE_VGATHERDPS256rmr 0xd80000098a0092 +#define FE_VGATHERDPD128rmr 0xd80000094a0092 +#define FE_VGATHERDPD256rmr 0xd8000009ca0092 +#define FE_VGATHERQPS128rmr 0xd80000090a0093 +#define FE_VGATHERQPS256rmr 0xd80000098a0093 +#define FE_VGATHERQPD128rmr 0xd80000094a0093 +#define FE_VGATHERQPD256rmr 0xd8000009ca0093 +#define FE_VFMADDSUB132PS128rrr 0xc00000010a0096 +#define FE_VFMADDSUB132PS128rrm 0xc00000010a0096 +#define FE_VFMADDSUB132PS256rrr 0xc00000018a0096 +#define FE_VFMADDSUB132PS256rrm 0xc00000018a0096 +#define FE_VFMADDSUB132PD128rrr 0xc00000014a0096 +#define FE_VFMADDSUB132PD128rrm 0xc00000014a0096 +#define FE_VFMADDSUB132PD256rrr 0xc0000001ca0096 +#define FE_VFMADDSUB132PD256rrm 0xc0000001ca0096 +#define FE_VFMSUBADD132PS128rrr 0xc00000010a0097 +#define FE_VFMSUBADD132PS128rrm 0xc00000010a0097 +#define FE_VFMSUBADD132PS256rrr 0xc00000018a0097 +#define FE_VFMSUBADD132PS256rrm 0xc00000018a0097 +#define FE_VFMSUBADD132PD128rrr 0xc00000014a0097 +#define FE_VFMSUBADD132PD128rrm 0xc00000014a0097 +#define FE_VFMSUBADD132PD256rrr 0xc0000001ca0097 +#define FE_VFMSUBADD132PD256rrm 0xc0000001ca0097 +#define FE_VFMADD132PS128rrr 0xc00000010a0098 +#define FE_VFMADD132PS128rrm 0xc00000010a0098 +#define FE_VFMADD132PS256rrr 0xc00000018a0098 +#define FE_VFMADD132PS256rrm 0xc00000018a0098 +#define FE_VFMADD132PD128rrr 0xc00000014a0098 +#define FE_VFMADD132PD128rrm 0xc00000014a0098 +#define FE_VFMADD132PD256rrr 0xc0000001ca0098 +#define FE_VFMADD132PD256rrm 0xc0000001ca0098 +#define FE_VFMADD132SSrrr 0xc00000010a0099 +#define FE_VFMADD132SSrrm 0xc00000010a0099 +#define FE_VFMADD132SDrrr 0xc00000014a0099 +#define FE_VFMADD132SDrrm 0xc00000014a0099 +#define FE_VFMSUB132PS128rrr 0xc00000010a009a +#define FE_VFMSUB132PS128rrm 0xc00000010a009a +#define FE_VFMSUB132PS256rrr 0xc00000018a009a +#define FE_VFMSUB132PS256rrm 0xc00000018a009a +#define FE_VFMSUB132PD128rrr 0xc00000014a009a +#define FE_VFMSUB132PD128rrm 0xc00000014a009a +#define FE_VFMSUB132PD256rrr 0xc0000001ca009a +#define FE_VFMSUB132PD256rrm 0xc0000001ca009a +#define FE_VFMSUB132SSrrr 0xc00000010a009b +#define FE_VFMSUB132SSrrm 0xc00000010a009b +#define FE_VFMSUB132SDrrr 0xc00000014a009b +#define FE_VFMSUB132SDrrm 0xc00000014a009b +#define FE_VFNMADD132PS128rrr 0xc00000010a009c +#define FE_VFNMADD132PS128rrm 0xc00000010a009c +#define FE_VFNMADD132PS256rrr 0xc00000018a009c +#define FE_VFNMADD132PS256rrm 0xc00000018a009c +#define FE_VFNMADD132PD128rrr 0xc00000014a009c +#define FE_VFNMADD132PD128rrm 0xc00000014a009c +#define FE_VFNMADD132PD256rrr 0xc0000001ca009c +#define FE_VFNMADD132PD256rrm 0xc0000001ca009c +#define FE_VFNMADD132SSrrr 0xc00000010a009d +#define FE_VFNMADD132SSrrm 0xc00000010a009d +#define FE_VFNMADD132SDrrr 0xc00000014a009d +#define FE_VFNMADD132SDrrm 0xc00000014a009d +#define FE_VFNMSUB132PS128rrr 0xc00000010a009e +#define FE_VFNMSUB132PS128rrm 0xc00000010a009e +#define FE_VFNMSUB132PS256rrr 0xc00000018a009e +#define FE_VFNMSUB132PS256rrm 0xc00000018a009e +#define FE_VFNMSUB132PD128rrr 0xc00000014a009e +#define FE_VFNMSUB132PD128rrm 0xc00000014a009e +#define FE_VFNMSUB132PD256rrr 0xc0000001ca009e +#define FE_VFNMSUB132PD256rrm 0xc0000001ca009e +#define FE_VFNMSUB132SSrrr 0xc00000010a009f +#define FE_VFNMSUB132SSrrm 0xc00000010a009f +#define FE_VFNMSUB132SDrrr 0xc00000014a009f +#define FE_VFNMSUB132SDrrm 0xc00000014a009f +#define FE_VFMADDSUB213PS128rrr 0xc00000010a00a6 +#define FE_VFMADDSUB213PS128rrm 0xc00000010a00a6 +#define FE_VFMADDSUB213PS256rrr 0xc00000018a00a6 +#define FE_VFMADDSUB213PS256rrm 0xc00000018a00a6 +#define FE_VFMADDSUB213PD128rrr 0xc00000014a00a6 +#define FE_VFMADDSUB213PD128rrm 0xc00000014a00a6 +#define FE_VFMADDSUB213PD256rrr 0xc0000001ca00a6 +#define FE_VFMADDSUB213PD256rrm 0xc0000001ca00a6 +#define FE_VFMSUBADD213PS128rrr 0xc00000010a00a7 +#define FE_VFMSUBADD213PS128rrm 0xc00000010a00a7 +#define FE_VFMSUBADD213PS256rrr 0xc00000018a00a7 +#define FE_VFMSUBADD213PS256rrm 0xc00000018a00a7 +#define FE_VFMSUBADD213PD128rrr 0xc00000014a00a7 +#define FE_VFMSUBADD213PD128rrm 0xc00000014a00a7 +#define FE_VFMSUBADD213PD256rrr 0xc0000001ca00a7 +#define FE_VFMSUBADD213PD256rrm 0xc0000001ca00a7 +#define FE_VFMADD213PS128rrr 0xc00000010a00a8 +#define FE_VFMADD213PS128rrm 0xc00000010a00a8 +#define FE_VFMADD213PS256rrr 0xc00000018a00a8 +#define FE_VFMADD213PS256rrm 0xc00000018a00a8 +#define FE_VFMADD213PD128rrr 0xc00000014a00a8 +#define FE_VFMADD213PD128rrm 0xc00000014a00a8 +#define FE_VFMADD213PD256rrr 0xc0000001ca00a8 +#define FE_VFMADD213PD256rrm 0xc0000001ca00a8 +#define FE_VFMADD213SSrrr 0xc00000010a00a9 +#define FE_VFMADD213SSrrm 0xc00000010a00a9 +#define FE_VFMADD213SDrrr 0xc00000014a00a9 +#define FE_VFMADD213SDrrm 0xc00000014a00a9 +#define FE_VFMSUB213PS128rrr 0xc00000010a00aa +#define FE_VFMSUB213PS128rrm 0xc00000010a00aa +#define FE_VFMSUB213PS256rrr 0xc00000018a00aa +#define FE_VFMSUB213PS256rrm 0xc00000018a00aa +#define FE_VFMSUB213PD128rrr 0xc00000014a00aa +#define FE_VFMSUB213PD128rrm 0xc00000014a00aa +#define FE_VFMSUB213PD256rrr 0xc0000001ca00aa +#define FE_VFMSUB213PD256rrm 0xc0000001ca00aa +#define FE_VFMSUB213SSrrr 0xc00000010a00ab +#define FE_VFMSUB213SSrrm 0xc00000010a00ab +#define FE_VFMSUB213SDrrr 0xc00000014a00ab +#define FE_VFMSUB213SDrrm 0xc00000014a00ab +#define FE_VFNMADD213PS128rrr 0xc00000010a00ac +#define FE_VFNMADD213PS128rrm 0xc00000010a00ac +#define FE_VFNMADD213PS256rrr 0xc00000018a00ac +#define FE_VFNMADD213PS256rrm 0xc00000018a00ac +#define FE_VFNMADD213PD128rrr 0xc00000014a00ac +#define FE_VFNMADD213PD128rrm 0xc00000014a00ac +#define FE_VFNMADD213PD256rrr 0xc0000001ca00ac +#define FE_VFNMADD213PD256rrm 0xc0000001ca00ac +#define FE_VFNMADD213SSrrr 0xc00000010a00ad +#define FE_VFNMADD213SSrrm 0xc00000010a00ad +#define FE_VFNMADD213SDrrr 0xc00000014a00ad +#define FE_VFNMADD213SDrrm 0xc00000014a00ad +#define FE_VFNMSUB213PS128rrr 0xc00000010a00ae +#define FE_VFNMSUB213PS128rrm 0xc00000010a00ae +#define FE_VFNMSUB213PS256rrr 0xc00000018a00ae +#define FE_VFNMSUB213PS256rrm 0xc00000018a00ae +#define FE_VFNMSUB213PD128rrr 0xc00000014a00ae +#define FE_VFNMSUB213PD128rrm 0xc00000014a00ae +#define FE_VFNMSUB213PD256rrr 0xc0000001ca00ae +#define FE_VFNMSUB213PD256rrm 0xc0000001ca00ae +#define FE_VFNMSUB213SSrrr 0xc00000010a00af +#define FE_VFNMSUB213SSrrm 0xc00000010a00af +#define FE_VFNMSUB213SDrrr 0xc00000014a00af +#define FE_VFNMSUB213SDrrm 0xc00000014a00af +#define FE_VFMADDSUB231PS128rrr 0xc00000010a00b6 +#define FE_VFMADDSUB231PS128rrm 0xc00000010a00b6 +#define FE_VFMADDSUB231PS256rrr 0xc00000018a00b6 +#define FE_VFMADDSUB231PS256rrm 0xc00000018a00b6 +#define FE_VFMADDSUB231PD128rrr 0xc00000014a00b6 +#define FE_VFMADDSUB231PD128rrm 0xc00000014a00b6 +#define FE_VFMADDSUB231PD256rrr 0xc0000001ca00b6 +#define FE_VFMADDSUB231PD256rrm 0xc0000001ca00b6 +#define FE_VFMSUBADD231PS128rrr 0xc00000010a00b7 +#define FE_VFMSUBADD231PS128rrm 0xc00000010a00b7 +#define FE_VFMSUBADD231PS256rrr 0xc00000018a00b7 +#define FE_VFMSUBADD231PS256rrm 0xc00000018a00b7 +#define FE_VFMSUBADD231PD128rrr 0xc00000014a00b7 +#define FE_VFMSUBADD231PD128rrm 0xc00000014a00b7 +#define FE_VFMSUBADD231PD256rrr 0xc0000001ca00b7 +#define FE_VFMSUBADD231PD256rrm 0xc0000001ca00b7 +#define FE_VFMADD231PS128rrr 0xc00000010a00b8 +#define FE_VFMADD231PS128rrm 0xc00000010a00b8 +#define FE_VFMADD231PS256rrr 0xc00000018a00b8 +#define FE_VFMADD231PS256rrm 0xc00000018a00b8 +#define FE_VFMADD231PD128rrr 0xc00000014a00b8 +#define FE_VFMADD231PD128rrm 0xc00000014a00b8 +#define FE_VFMADD231PD256rrr 0xc0000001ca00b8 +#define FE_VFMADD231PD256rrm 0xc0000001ca00b8 +#define FE_VFMADD231SSrrr 0xc00000010a00b9 +#define FE_VFMADD231SSrrm 0xc00000010a00b9 +#define FE_VFMADD231SDrrr 0xc00000014a00b9 +#define FE_VFMADD231SDrrm 0xc00000014a00b9 +#define FE_VFMSUB231PS128rrr 0xc00000010a00ba +#define FE_VFMSUB231PS128rrm 0xc00000010a00ba +#define FE_VFMSUB231PS256rrr 0xc00000018a00ba +#define FE_VFMSUB231PS256rrm 0xc00000018a00ba +#define FE_VFMSUB231PD128rrr 0xc00000014a00ba +#define FE_VFMSUB231PD128rrm 0xc00000014a00ba +#define FE_VFMSUB231PD256rrr 0xc0000001ca00ba +#define FE_VFMSUB231PD256rrm 0xc0000001ca00ba +#define FE_VFMSUB231SSrrr 0xc00000010a00bb +#define FE_VFMSUB231SSrrm 0xc00000010a00bb +#define FE_VFMSUB231SDrrr 0xc00000014a00bb +#define FE_VFMSUB231SDrrm 0xc00000014a00bb +#define FE_VFNMADD231PS128rrr 0xc00000010a00bc +#define FE_VFNMADD231PS128rrm 0xc00000010a00bc +#define FE_VFNMADD231PS256rrr 0xc00000018a00bc +#define FE_VFNMADD231PS256rrm 0xc00000018a00bc +#define FE_VFNMADD231PD128rrr 0xc00000014a00bc +#define FE_VFNMADD231PD128rrm 0xc00000014a00bc +#define FE_VFNMADD231PD256rrr 0xc0000001ca00bc +#define FE_VFNMADD231PD256rrm 0xc0000001ca00bc +#define FE_VFNMADD231SSrrr 0xc00000010a00bd +#define FE_VFNMADD231SSrrm 0xc00000010a00bd +#define FE_VFNMADD231SDrrr 0xc00000014a00bd +#define FE_VFNMADD231SDrrm 0xc00000014a00bd +#define FE_VFNMSUB231PS128rrr 0xc00000010a00be +#define FE_VFNMSUB231PS128rrm 0xc00000010a00be +#define FE_VFNMSUB231PS256rrr 0xc00000018a00be +#define FE_VFNMSUB231PS256rrm 0xc00000018a00be +#define FE_VFNMSUB231PD128rrr 0xc00000014a00be +#define FE_VFNMSUB231PD128rrm 0xc00000014a00be +#define FE_VFNMSUB231PD256rrr 0xc0000001ca00be +#define FE_VFNMSUB231PD256rrm 0xc0000001ca00be +#define FE_VFNMSUB231SSrrr 0xc00000010a00bf +#define FE_VFNMSUB231SSrrm 0xc00000010a00bf +#define FE_VFNMSUB231SDrrr 0xc00000014a00bf +#define FE_VFNMSUB231SDrrm 0xc00000014a00bf +#define FE_VPERMQ256rmi 0x50800001cb0000 +#define FE_VPERMQ256rri 0x50800001cb0000 +#define FE_VPERMPD256rmi 0x50800001cb0001 +#define FE_VPERMPD256rri 0x50800001cb0001 +#define FE_VPBLENDD128rrmi 0xc88000010b0002 +#define FE_VPBLENDD128rrri 0xc88000010b0002 +#define FE_VPBLENDD256rrmi 0xc88000018b0002 +#define FE_VPBLENDD256rrri 0xc88000018b0002 +#define FE_VPERMILPS128rmi 0x508000010b0004 +#define FE_VPERMILPS128rri 0x508000010b0004 +#define FE_VPERMILPS256rmi 0x508000018b0004 +#define FE_VPERMILPS256rri 0x508000018b0004 +#define FE_VPERMILPD128rmi 0x508000010b0005 +#define FE_VPERMILPD128rri 0x508000010b0005 +#define FE_VPERMILPD256rmi 0x508000018b0005 +#define FE_VPERMILPD256rri 0x508000018b0005 +#define FE_VPERM2F128_256rrmi 0xc88000018b0006 +#define FE_VPERM2F128_256rrri 0xc88000018b0006 +#define FE_VROUNDPS128rmi 0x508000010b0008 +#define FE_VROUNDPS128rri 0x508000010b0008 +#define FE_VROUNDPS256rmi 0x508000018b0008 +#define FE_VROUNDPS256rri 0x508000018b0008 +#define FE_VROUNDPD128rmi 0x508000010b0009 +#define FE_VROUNDPD128rri 0x508000010b0009 +#define FE_VROUNDPD256rmi 0x508000018b0009 +#define FE_VROUNDPD256rri 0x508000018b0009 +#define FE_VROUNDSSrrmi 0xc88000010b000a +#define FE_VROUNDSSrrri 0xc88000010b000a +#define FE_VROUNDSDrrmi 0xc88000010b000b +#define FE_VROUNDSDrrri 0xc88000010b000b +#define FE_VBLENDPS128rrmi 0xc88000010b000c +#define FE_VBLENDPS128rrri 0xc88000010b000c +#define FE_VBLENDPS256rrmi 0xc88000018b000c +#define FE_VBLENDPS256rrri 0xc88000018b000c +#define FE_VBLENDPD128rrmi 0xc88000010b000d +#define FE_VBLENDPD128rrri 0xc88000010b000d +#define FE_VBLENDPD256rrmi 0xc88000018b000d +#define FE_VBLENDPD256rrri 0xc88000018b000d +#define FE_VPBLENDW128rrmi 0xc88000010b000e +#define FE_VPBLENDW128rrri 0xc88000010b000e +#define FE_VPBLENDW256rrmi 0xc88000018b000e +#define FE_VPBLENDW256rrri 0xc88000018b000e +#define FE_VPALIGNR128rrmi 0xc88000010b000f +#define FE_VPALIGNR128rrri 0xc88000010b000f +#define FE_VPALIGNR256rrmi 0xc88000018b000f +#define FE_VPALIGNR256rrri 0xc88000018b000f +#define FE_VPEXTRBmri 0x488000010b0014 +#define FE_VPEXTRBrri 0x488000010b0014 +#define FE_VPEXTRWmri 0x488000010b0015 +#define FE_VPEXTRDrri 0x488000010b0016 +#define FE_VPEXTRDmri 0x488000010b0016 +#define FE_VPEXTRQrri 0x488000014b0016 +#define FE_VPEXTRQmri 0x488000014b0016 +#define FE_VEXTRACTPSrri 0x488000010b0017 +#define FE_VEXTRACTPSmri 0x488000010b0017 +#define FE_VINSERTF128rrmi 0xc88000018b0018 +#define FE_VINSERTF128rrri 0xc88000018b0018 +#define FE_VEXTRACTF128rri 0x488000018b0019 +#define FE_VEXTRACTF128mri 0x488000018b0019 +#define FE_VCVTPS2PH128rri 0x488000010b001d +#define FE_VCVTPS2PH128mri 0x488000010b001d +#define FE_VCVTPS2PH256rri 0x488000018b001d +#define FE_VCVTPS2PH256mri 0x488000018b001d +#define FE_VPINSRBrrmi 0xc88000010b0020 +#define FE_VPINSRBrrri 0xc88000010b0020 +#define FE_VINSERTPSrrmi 0xc88000010b0021 +#define FE_VINSERTPSrrri 0xc88000010b0021 +#define FE_VPINSRDrrmi 0xc88000010b0022 +#define FE_VPINSRDrrri 0xc88000010b0022 +#define FE_VPINSRQrrmi 0xc88000014b0022 +#define FE_VPINSRQrrri 0xc88000014b0022 +#define FE_VINSERTI128rrmi 0xc88000018b0038 +#define FE_VINSERTI128rrri 0xc88000018b0038 +#define FE_VEXTRACTI128rri 0x488000018b0039 +#define FE_VEXTRACTI128mri 0x488000018b0039 +#define FE_VDPPS128rrmi 0xc88000010b0040 +#define FE_VDPPS128rrri 0xc88000010b0040 +#define FE_VDPPS256rrmi 0xc88000018b0040 +#define FE_VDPPS256rrri 0xc88000018b0040 +#define FE_VDPPD128rrmi 0xc88000010b0041 +#define FE_VDPPD128rrri 0xc88000010b0041 +#define FE_VMPSADBW128rrmi 0xc88000010b0042 +#define FE_VMPSADBW128rrri 0xc88000010b0042 +#define FE_VMPSADBW256rrmi 0xc88000018b0042 +#define FE_VMPSADBW256rrri 0xc88000018b0042 +#define FE_VPCLMULQDQ128rrmi 0xc88000010b0044 +#define FE_VPCLMULQDQ128rrri 0xc88000010b0044 +#define FE_VPCLMULQDQ256rrmi 0xc88000018b0044 +#define FE_VPCLMULQDQ256rrri 0xc88000018b0044 +#define FE_VPERM2I128_256rrmi 0xc88000018b0046 +#define FE_VPERM2I128_256rrri 0xc88000018b0046 +#define FE_VBLENDVPS128rrmr 0xd08000010b004a +#define FE_VBLENDVPS128rrrr 0xd08000010b004a +#define FE_VBLENDVPS256rrmr 0xd08000018b004a +#define FE_VBLENDVPS256rrrr 0xd08000018b004a +#define FE_VBLENDVPD128rrmr 0xd08000010b004b +#define FE_VBLENDVPD128rrrr 0xd08000010b004b +#define FE_VBLENDVPD256rrmr 0xd08000018b004b +#define FE_VBLENDVPD256rrrr 0xd08000018b004b +#define FE_VPBLENDVB128rrmr 0xd08000010b004c +#define FE_VPBLENDVB128rrrr 0xd08000010b004c +#define FE_VPBLENDVB256rrmr 0xd08000018b004c +#define FE_VPBLENDVB256rrrr 0xd08000018b004c +#define FE_VPCMPESTRMrmi 0x508000010b0060 +#define FE_VPCMPESTRMrri 0x508000010b0060 +#define FE_VPCMPESTRIrmi 0x508000010b0061 +#define FE_VPCMPESTRIrri 0x508000010b0061 +#define FE_VPCMPISTRMrmi 0x508000010b0062 +#define FE_VPCMPISTRMrri 0x508000010b0062 +#define FE_VPCMPISTRIrmi 0x508000010b0063 +#define FE_VPCMPISTRIrri 0x508000010b0063 +#define FE_ANDN32rrr 0xc00000010200f2 +#define FE_ANDN32rrm 0xc00000010200f2 +#define FE_ANDN64rrr 0xc00000014200f2 +#define FE_ANDN64rrm 0xc00000014200f2 +#define FE_BLSR32rm 0xe00000010201f3 +#define FE_BLSR32rr 0xe00000010201f3 +#define FE_BLSR64rm 0xe00000014201f3 +#define FE_BLSR64rr 0xe00000014201f3 +#define FE_BLSMSK32rm 0xe00000010202f3 +#define FE_BLSMSK32rr 0xe00000010202f3 +#define FE_BLSMSK64rm 0xe00000014202f3 +#define FE_BLSMSK64rr 0xe00000014202f3 +#define FE_BLSI32rm 0xe00000010203f3 +#define FE_BLSI32rr 0xe00000010203f3 +#define FE_BLSI64rm 0xe00000014203f3 +#define FE_BLSI64rr 0xe00000014203f3 +#define FE_BEXTR32rmr 0xd80000010200f7 +#define FE_BEXTR32rrr 0xd80000010200f7 +#define FE_BEXTR64rmr 0xd80000014200f7 +#define FE_BEXTR64rrr 0xd80000014200f7 +#define FE_RORX32rmi 0x508000011300f0 +#define FE_RORX32rri 0x508000011300f0 +#define FE_RORX64rmi 0x508000015300f0 +#define FE_RORX64rri 0x508000015300f0 +#define FE_BZHI32rmr 0xd80000010200f5 +#define FE_BZHI32rrr 0xd80000010200f5 +#define FE_BZHI64rmr 0xd80000014200f5 +#define FE_BZHI64rrr 0xd80000014200f5 +#define FE_PDEP32rrr 0xc00000011200f5 +#define FE_PDEP32rrm 0xc00000011200f5 +#define FE_PDEP64rrr 0xc00000015200f5 +#define FE_PDEP64rrm 0xc00000015200f5 +#define FE_PEXT32rrr 0xc00000012200f5 +#define FE_PEXT32rrm 0xc00000012200f5 +#define FE_PEXT64rrr 0xc00000016200f5 +#define FE_PEXT64rrm 0xc00000016200f5 +#define FE_MULX32rrr 0xc00000011200f6 +#define FE_MULX32rrm 0xc00000011200f6 +#define FE_MULX64rrr 0xc00000015200f6 +#define FE_MULX64rrm 0xc00000015200f6 +#define FE_SHLX32rmr 0xd80000010a00f7 +#define FE_SHLX32rrr 0xd80000010a00f7 +#define FE_SHLX64rmr 0xd80000014a00f7 +#define FE_SHLX64rrr 0xd80000014a00f7 +#define FE_SHRX32rmr 0xd80000011200f7 +#define FE_SHRX32rrr 0xd80000011200f7 +#define FE_SHRX64rmr 0xd80000015200f7 +#define FE_SHRX64rrr 0xd80000015200f7 +#define FE_SARX32rmr 0xd80000012200f7 +#define FE_SARX32rrr 0xd80000012200f7 +#define FE_SARX64rmr 0xd80000016200f7 +#define FE_SARX64rrr 0xd80000016200f7 +#define FE_ADCX32rm 0x380000000a00f6 +#define FE_ADCX32rr 0x380000000a00f6 +#define FE_ADCX64rm 0x380000004a00f6 +#define FE_ADCX64rr 0x380000004a00f6 +#define FE_ADOX32rm 0x380000002200f6 +#define FE_ADOX32rr 0x380000002200f6 +#define FE_ADOX64rm 0x380000006200f6 +#define FE_ADOX64rr 0x380000006200f6 +#define FE_FADDm32 0x100000000000d8 +#define FE_FMULm32 0x100000000001d8 +#define FE_FCOMm32 0x100000000002d8 +#define FE_FCOMPm32 0x100000000003d8 +#define FE_FSUBm32 0x100000000004d8 +#define FE_FSUBRm32 0x100000000005d8 +#define FE_FDIVm32 0x100000000006d8 +#define FE_FDIVRm32 0x100000000007d8 +#define FE_FADDrr 0xca600000000000d8 +#define FE_FMULrr 0xcb600000000001d8 +#define FE_FCOMrr 0x600000000002d8 +#define FE_FCOMPrr 0x600000000003d8 +#define FE_FSUBrr 0xcc600000000004d8 +#define FE_FSUBRrr 0xcd600000000005d8 +#define FE_FDIVrr 0xce600000000006d8 +#define FE_FDIVRrr 0xcf600000000007d8 +#define FE_FLDm32 0x100000000000d9 +#define FE_FSTm32 0x100000000002d9 +#define FE_FSTPm32 0x100000000003d9 +#define FE_FLDENVm 0x100000000004d9 +#define FE_FLDCWm 0x100000000005d9 +#define FE_FSTENVm 0x100000000006d9 +#define FE_FSTCWm 0x100000000007d9 +#define FE_FLDr 0x100000000000d9 +#define FE_FXCHr 0x100000000001d9 +#define FE_FNOP 0x800000000d0d9 +#define FE_FCHS 0x800000000e0d9 +#define FE_FABS 0x800000000e1d9 +#define FE_FTST 0x800000000e4d9 +#define FE_FXAM 0x800000000e5d9 +#define FE_FLD1 0x800000000e8d9 +#define FE_FLDL2T 0x800000000e9d9 +#define FE_FLDL2E 0x800000000ead9 +#define FE_FLDPI 0x800000000ebd9 +#define FE_FLDLG2 0x800000000ecd9 +#define FE_FLDLN2 0x800000000edd9 +#define FE_FLDZ 0x800000000eed9 +#define FE_F2XM1 0x800000000f0d9 +#define FE_FYL2X 0x800000000f1d9 +#define FE_FPTAN 0x800000000f2d9 +#define FE_FPATAN 0x800000000f3d9 +#define FE_FXTRACT 0x800000000f4d9 +#define FE_FPREM1 0x800000000f5d9 +#define FE_FDECSTP 0x800000000f6d9 +#define FE_FINCSTP 0x800000000f7d9 +#define FE_FPREM 0x800000000f8d9 +#define FE_FYL2XP1 0x800000000f9d9 +#define FE_FSQRT 0x800000000fad9 +#define FE_FSINCOS 0x800000000fbd9 +#define FE_FRNDINT 0x800000000fcd9 +#define FE_FSCALE 0x800000000fdd9 +#define FE_FSIN 0x800000000fed9 +#define FE_FCOS 0x800000000ffd9 +#define FE_FIADDm32 0x100000000000da +#define FE_FIMULm32 0x100000000001da +#define FE_FICOMm32 0x100000000002da +#define FE_FICOMPm32 0x100000000003da +#define FE_FISUBm32 0x100000000004da +#define FE_FISUBRm32 0x100000000005da +#define FE_FIDIVm32 0x100000000006da +#define FE_FIDIVRm32 0x100000000007da +#define FE_FCMOVBr 0x100000000000da +#define FE_FCMOVEr 0x100000000001da +#define FE_FCMOVBEr 0x100000000002da +#define FE_FCMOVUr 0x100000000003da +#define FE_FUCOMPP 0x800000000e9da +#define FE_FILDm32 0x100000000000db +#define FE_FISTTPm32 0x100000000001db +#define FE_FISTm32 0x100000000002db +#define FE_FISTPm32 0x100000000003db +#define FE_FLDm80 0x100000000005db +#define FE_FSTPm80 0x100000000007db +#define FE_FCMOVNBr 0x100000000000db +#define FE_FCMOVNEr 0x100000000001db +#define FE_FCMOVNBEr 0x100000000002db +#define FE_FCMOVNUr 0x100000000003db +#define FE_FCLEX 0x800000000e2db +#define FE_FINIT 0x800000000e3db +#define FE_FUCOMIr 0x100000000005db +#define FE_FCOMIr 0x100000000006db +#define FE_FADDm64 0x100000000000dc +#define FE_FMULm64 0x100000000001dc +#define FE_FCOMm64 0x100000000002dc +#define FE_FCOMPm64 0x100000000003dc +#define FE_FSUBm64 0x100000000004dc +#define FE_FSUBRm64 0x100000000005dc +#define FE_FDIVm64 0x100000000006dc +#define FE_FDIVRm64 0x100000000007dc +#define FE_FLDm64 0x100000000000dd +#define FE_FISTTPm64 0x100000000001dd +#define FE_FSTm64 0x100000000002dd +#define FE_FSTPm64 0x100000000003dd +#define FE_FRSTORm 0x100000000004dd +#define FE_FSAVEm 0x100000000006dd +#define FE_FSTSWm 0x100000000007dd +#define FE_FFREEr 0x100000000000dd +#define FE_FSTr 0x100000000002dd +#define FE_FSTPr 0x100000000003dd +#define FE_FUCOMr 0x100000000004dd +#define FE_FUCOMPr 0x100000000005dd +#define FE_FIADDm16 0x100000000000de +#define FE_FIMULm16 0x100000000001de +#define FE_FICOMm16 0x100000000002de +#define FE_FICOMPm16 0x100000000003de +#define FE_FISUBm16 0x100000000004de +#define FE_FISUBRm16 0x100000000005de +#define FE_FIDIVm16 0x100000000006de +#define FE_FIDIVRm16 0x100000000007de +#define FE_FADDPrr 0x680000000000de +#define FE_FMULPrr 0x680000000001de +#define FE_FCOMPP 0x800000000d9de +#define FE_FSUBRPrr 0x680000000004de +#define FE_FSUBPrr 0x680000000005de +#define FE_FDIVRPrr 0x680000000006de +#define FE_FDIVPrr 0x680000000007de +#define FE_FILDm16 0x100000000000df +#define FE_FISTTPm16 0x100000000001df +#define FE_FISTm16 0x100000000002df +#define FE_FISTPm16 0x100000000003df +#define FE_FBLDm 0x100000000004df +#define FE_FILDm64 0x100000000005df +#define FE_FBSTPm 0x100000000006df +#define FE_FISTPm64 0x100000000007df +#define FE_FSTSWr 0xa000000000e0df +#define FE_FUCOMIPrr 0x600000000005df +#define FE_FCOMIPrr 0x600000000006df +#define FE_RSTORSSPm 0x10000000210501 +#define FE_SETSSBSY 0x800000021e801 +#define FE_SAVEPREVSSP 0x800000021ea01 +#define FE_RDSSP32r 0x1000000021011e +#define FE_RDSSP64r 0x1000000061011e +#define FE_ENDBR64 0x800000021fa1e +#define FE_ENDBR32 0x800000021fb1e +#define FE_WRUSS32mr 0x300000000a00f5 +#define FE_WRUSS64mr 0x300000004a00f5 +#define FE_WRSS32mr 0x300000000200f6 +#define FE_WRSS64mr 0x300000004200f6 +#define FE_CLRSSBSYm 0x100000002106ae +#define FE_INCSSP32r 0x100000002105ae +#define FE_INCSSP64r 0x100000006105ae +#define FE_CLDEMOTEm 0x1000000001001c +#define FE_REP_MONTMUL 0x800000021c0a6 +#define FE_REP_XSHA1 0x800000021c8a6 +#define FE_REP_XSHA256 0x800000021d0a6 +#define FE_XSTORE 0x800000001c0a7 +#define FE_REP_XSTORE 0x800000021c0a7 +#define FE_REP_XCRYPTECB 0x800000021c8a7 +#define FE_REP_XCRYPTCBC 0x800000021d0a7 +#define FE_REP_XCRYPTCTR 0x800000021d8a7 +#define FE_REP_XCRYPTCFB 0x800000021e0a7 +#define FE_REP_XCRYPTOFB 0x800000021e8a7 +#define FE_INVEPTrm 0x380000000a0080 +#define FE_INVVPIDrm 0x380000000a0081 +#define FE_VMCALL 0x800000001c101 +#define FE_VMCLEARm 0x100000000906c7 +#define FE_VMFUNC 0x800000001d401 +#define FE_VMLAUNCH 0x800000001c201 +#define FE_VMRESUME 0x800000001c301 +#define FE_VMPTRLDm 0x100000000106c7 +#define FE_VMPTRSTm 0x100000000107c7 +#define FE_VMREADmr 0x30000000010078 +#define FE_VMREADrr 0x30000000010078 +#define FE_VMWRITErm 0x38000000010079 +#define FE_VMWRITErr 0x38000000010079 +#define FE_VMXOFF 0x800000001c401 +#define FE_VMXONm 0x100000002106c7 +#define FE_TDCALL 0x800000009cc01 +#define FE_SEAMRET 0x800000009cd01 +#define FE_SEAMOPS 0x800000009ce01 +#define FE_SEAMCALL 0x800000009cf01 +#define FE_CLZERO16r 0xa000000009fc01 +#define FE_CLZERO32r 0xa000000001fc01 +#define FE_CLZERO64r 0xa000000041fc01 +#define FE_RDPRU 0x800000001fd01 +#define FE_VMRUN 0x800000001d801 +#define FE_VMMCALL 0x800000001d901 +#define FE_VMGEXIT 0x800000021d901 +#define FE_VMLOAD 0x800000001da01 +#define FE_VMSAVE 0x800000001db01 +#define FE_STGI 0x800000001dc01 +#define FE_CLGI 0x800000001dd01 +#define FE_SKINIT 0x800000001de01 +#define FE_INVLPGA 0x800000001df01 +#define FE_MONITORX 0x800000001fa01 +#define FE_MCOMMIT 0x800000021fa01 +#define FE_MWAITX 0x800000001fb01 +#define FE_INVLPGB 0x800000001fe01 +#define FE_TLBSYNC 0x800000001ff01 +#define FE_RMPADJUST 0x800000021fe01 +#define FE_RMPUPDATE 0x800000011fe01 +#define FE_PSMASH 0x800000021ff01 +#define FE_PVALIDATE 0x800000011ff01 +#define FE_TPAUSEr 0x100000000906ae +#define FE_UMONITOR32r 0x100000002106ae +#define FE_UMONITOR64r 0x100000006106ae +#define FE_UMWAITr 0x100000001106ae +#define FE_PTWRITE32m 0x100000002104ae +#define FE_PTWRITE32r 0x100000002104ae +#define FE_PTWRITE64m 0x100000006104ae +#define FE_PTWRITE64r 0x100000006104ae +#define FE_GF2P8MULBrm 0x380000000a00cf +#define FE_GF2P8MULBrr 0x380000000a00cf +#define FE_GF2P8AFFINEQBrmi 0x508000000b00ce +#define FE_GF2P8AFFINEQBrri 0x508000000b00ce +#define FE_GF2P8AFFINEINVQBrmi 0x508000000b00cf +#define FE_GF2P8AFFINEINVQBrri 0x508000000b00cf +#define FE_VGF2P8MULB128rrr 0xc00000010a00cf +#define FE_VGF2P8MULB128rrm 0xc00000010a00cf +#define FE_VGF2P8MULB256rrr 0xc00000018a00cf +#define FE_VGF2P8MULB256rrm 0xc00000018a00cf +#define FE_VGF2P8AFFINEQB128rrmi 0xc88000014b00ce +#define FE_VGF2P8AFFINEQB128rrri 0xc88000014b00ce +#define FE_VGF2P8AFFINEQB256rrmi 0xc8800001cb00ce +#define FE_VGF2P8AFFINEQB256rrri 0xc8800001cb00ce +#define FE_VGF2P8AFFINEINVQB128rrmi 0xc88000014b00cf +#define FE_VGF2P8AFFINEINVQB128rrri 0xc88000014b00cf +#define FE_VGF2P8AFFINEINVQB256rrmi 0xc8800001cb00cf +#define FE_VGF2P8AFFINEINVQB256rrri 0xc8800001cb00cf +#define FE_ENQCMD32rm 0x380000001200f8 +#define FE_ENQCMD64rm 0x380000005200f8 +#define FE_ENQCMDS32rm 0x380000002200f8 +#define FE_ENQCMDS64rm 0x380000006200f8 +#define FE_PCONFIG 0x800000001c501 +#define FE_WBNOINVD 0x8000000210009 +#define FE_RDPKRU 0x800000001ee01 +#define FE_WRPKRU 0x800000001ef01 +#define FE_RDFSBASE32r 0x100000002100ae +#define FE_RDFSBASE64r 0x100000006100ae +#define FE_RDGSBASE32r 0x100000002101ae +#define FE_RDGSBASE64r 0x100000006101ae +#define FE_WRFSBASE32r 0x100000002102ae +#define FE_WRFSBASE64r 0x100000006102ae +#define FE_WRGSBASE32r 0x100000002103ae +#define FE_WRGSBASE64r 0x100000006103ae +#define FE_XSAVE32m 0x100000000104ae +#define FE_XSAVE64m 0x100000004104ae +#define FE_XRSTOR32m 0x100000000105ae +#define FE_XRSTOR64m 0x100000004105ae +#define FE_XSAVEOPT32m 0x100000000106ae +#define FE_XSAVEOPT64m 0x100000004106ae +#define FE_CLWBm 0x100000000906ae +#define FE_CLFLUSHm 0x100000000107ae +#define FE_CLFLUSHOPTm 0x100000000907ae +#define FE_XRSTORS32m 0x100000000103c7 +#define FE_XRSTORS64m 0x100000004103c7 +#define FE_XSAVEC32m 0x100000000104c7 +#define FE_XSAVEC64m 0x100000004104c7 +#define FE_XSAVES32m 0x100000000105c7 +#define FE_XSAVES64m 0x100000004105c7 +#define FE_RDRAND16r 0x100000000906c7 +#define FE_RDRAND32r 0x100000000106c7 +#define FE_RDRAND64r 0x100000004106c7 +#define FE_RDSEED16r 0x100000000907c7 +#define FE_RDSEED32r 0x100000000107c7 +#define FE_RDSEED64r 0x100000004107c7 +#define FE_RDPIDr 0x100000002107c7 +#define FE_INVPCIDrm 0x380000000a0082 +#define FE_SHA1NEXTErm 0x380000000200c8 +#define FE_SHA1NEXTErr 0x380000000200c8 +#define FE_SHA1MSG1rm 0x380000000200c9 +#define FE_SHA1MSG1rr 0x380000000200c9 +#define FE_SHA1MSG2rm 0x380000000200ca +#define FE_SHA1MSG2rr 0x380000000200ca +#define FE_SHA256RNDS2rmr 0x400000000200cb +#define FE_SHA256RNDS2rrr 0x400000000200cb +#define FE_SHA256MSG1rm 0x380000000200cc +#define FE_SHA256MSG1rr 0x380000000200cc +#define FE_SHA256MSG2rm 0x380000000200cd +#define FE_SHA256MSG2rr 0x380000000200cd +#define FE_SHA1RNDS4rmi 0x508000000300cc +#define FE_SHA1RNDS4rri 0x508000000300cc +#define FE_XSUSLDTRK 0x800000011e801 +#define FE_XRESLDTRK 0x800000011e901 +#define FE_VPDPBUUD128rrr 0xc0000001020050 +#define FE_VPDPBUUD128rrm 0xc0000001020050 +#define FE_VPDPBUUD256rrr 0xc0000001820050 +#define FE_VPDPBUUD256rrm 0xc0000001820050 +#define FE_VPDPBUSD128rrr 0xc00000010a0050 +#define FE_VPDPBUSD128rrm 0xc00000010a0050 +#define FE_VPDPBUSD256rrr 0xc00000018a0050 +#define FE_VPDPBUSD256rrm 0xc00000018a0050 +#define FE_VPDPBSUD128rrr 0xc0000001220050 +#define FE_VPDPBSUD128rrm 0xc0000001220050 +#define FE_VPDPBSUD256rrr 0xc0000001a20050 +#define FE_VPDPBSUD256rrm 0xc0000001a20050 +#define FE_VPDPBSSD128rrr 0xc0000001120050 +#define FE_VPDPBSSD128rrm 0xc0000001120050 +#define FE_VPDPBSSD256rrr 0xc0000001920050 +#define FE_VPDPBSSD256rrm 0xc0000001920050 +#define FE_VPDPBUUDS128rrr 0xc0000001020051 +#define FE_VPDPBUUDS128rrm 0xc0000001020051 +#define FE_VPDPBUUDS256rrr 0xc0000001820051 +#define FE_VPDPBUUDS256rrm 0xc0000001820051 +#define FE_VPDPBUSDS128rrr 0xc00000010a0051 +#define FE_VPDPBUSDS128rrm 0xc00000010a0051 +#define FE_VPDPBUSDS256rrr 0xc00000018a0051 +#define FE_VPDPBUSDS256rrm 0xc00000018a0051 +#define FE_VPDPBSUDS128rrr 0xc0000001220051 +#define FE_VPDPBSUDS128rrm 0xc0000001220051 +#define FE_VPDPBSUDS256rrr 0xc0000001a20051 +#define FE_VPDPBSUDS256rrm 0xc0000001a20051 +#define FE_VPDPBSSDS128rrr 0xc0000001120051 +#define FE_VPDPBSSDS128rrm 0xc0000001120051 +#define FE_VPDPBSSDS256rrr 0xc0000001920051 +#define FE_VPDPBSSDS256rrm 0xc0000001920051 +#define FE_VPDPWSSD128rrr 0xc00000010a0052 +#define FE_VPDPWSSD128rrm 0xc00000010a0052 +#define FE_VPDPWSSD256rrr 0xc00000018a0052 +#define FE_VPDPWSSD256rrm 0xc00000018a0052 +#define FE_VPDPWSSDS128rrr 0xc00000010a0053 +#define FE_VPDPWSSDS128rrm 0xc00000010a0053 +#define FE_VPDPWSSDS256rrr 0xc00000018a0053 +#define FE_VPDPWSSDS256rrm 0xc00000018a0053 +#define FE_VCVTNEOPH2PS128rm 0x380000010200b0 +#define FE_VCVTNEOPH2PS256rm 0x380000018200b0 +#define FE_VCVTNEEPH2PS128rm 0x380000010a00b0 +#define FE_VCVTNEEPH2PS256rm 0x380000018a00b0 +#define FE_VCVTNEEBF162PS128rm 0x380000012200b0 +#define FE_VCVTNEEBF162PS256rm 0x38000001a200b0 +#define FE_VCVTNEOBF162PS128rm 0x380000011200b0 +#define FE_VCVTNEOBF162PS256rm 0x380000019200b0 +#define FE_VBCSTNESH2PS128rm 0x380000010a00b1 +#define FE_VBCSTNESH2PS256rm 0x380000018a00b1 +#define FE_VBCSTNEBF162PS128rm 0x380000012200b1 +#define FE_VBCSTNEBF162PS256rm 0x38000001a200b1 +#define FE_VCVTNEPS2BF16_128rm 0x38000001220072 +#define FE_VCVTNEPS2BF16_128rr 0x38000001220072 +#define FE_VCVTNEPS2BF16_256rm 0x38000001a20072 +#define FE_VCVTNEPS2BF16_256rr 0x38000001a20072 +#define FE_VPMADD52LUQ128rrr 0xc00000014a00b4 +#define FE_VPMADD52LUQ128rrm 0xc00000014a00b4 +#define FE_VPMADD52LUQ256rrr 0xc0000001ca00b4 +#define FE_VPMADD52LUQ256rrm 0xc0000001ca00b4 +#define FE_VPMADD52HUQ128rrr 0xc00000014a00b5 +#define FE_VPMADD52HUQ128rrm 0xc00000014a00b5 +#define FE_VPMADD52HUQ256rrr 0xc0000001ca00b5 +#define FE_VPMADD52HUQ256rrm 0xc0000001ca00b5 +#define FE_HRESETi 0x7080000023c0f0 +#define FE_SERIALIZE 0x800000001e801 +#define FE_UIRET 0x800000021ec01 +#define FE_TESTUI 0x800000021ed01 +#define FE_CLUI 0x800000021ee01 +#define FE_STUI 0x800000021ef01 +#define FE_SENDUIPIr 0x100000002106c7 +#define FE_WRMSRNS 0x800000001c601 +#define FE_RDMSRLIST 0x800000011c601 +#define FE_WRMSRLIST 0x800000021c601 +#define FE_AADD32mr 0x300000000200fc +#define FE_AADD64mr 0x300000004200fc +#define FE_AAND32mr 0x300000000a00fc +#define FE_AAND64mr 0x300000004a00fc +#define FE_AXOR32mr 0x300000002200fc +#define FE_AXOR64mr 0x300000006200fc +#define FE_AOR32mr 0x300000001200fc +#define FE_AOR64mr 0x300000005200fc +#define FE_CMPOXADD32mrr 0xf80000010a00e0 +#define FE_CMPOXADD64mrr 0xf80000014a00e0 +#define FE_CMPNOXADD32mrr 0xf80000010a00e1 +#define FE_CMPNOXADD64mrr 0xf80000014a00e1 +#define FE_CMPBXADD32mrr 0xf80000010a00e2 +#define FE_CMPBXADD64mrr 0xf80000014a00e2 +#define FE_CMPNBXADD32mrr 0xf80000010a00e3 +#define FE_CMPNBXADD64mrr 0xf80000014a00e3 +#define FE_CMPZXADD32mrr 0xf80000010a00e4 +#define FE_CMPZXADD64mrr 0xf80000014a00e4 +#define FE_CMPNZXADD32mrr 0xf80000010a00e5 +#define FE_CMPNZXADD64mrr 0xf80000014a00e5 +#define FE_CMPBEXADD32mrr 0xf80000010a00e6 +#define FE_CMPBEXADD64mrr 0xf80000014a00e6 +#define FE_CMPNBEXADD32mrr 0xf80000010a00e7 +#define FE_CMPNBEXADD64mrr 0xf80000014a00e7 +#define FE_CMPSXADD32mrr 0xf80000010a00e8 +#define FE_CMPSXADD64mrr 0xf80000014a00e8 +#define FE_CMPNSXADD32mrr 0xf80000010a00e9 +#define FE_CMPNSXADD64mrr 0xf80000014a00e9 +#define FE_CMPPXADD32mrr 0xf80000010a00ea +#define FE_CMPPXADD64mrr 0xf80000014a00ea +#define FE_CMPNPXADD32mrr 0xf80000010a00eb +#define FE_CMPNPXADD64mrr 0xf80000014a00eb +#define FE_CMPLXADD32mrr 0xf80000010a00ec +#define FE_CMPLXADD64mrr 0xf80000014a00ec +#define FE_CMPNLXADD32mrr 0xf80000010a00ed +#define FE_CMPNLXADD64mrr 0xf80000014a00ed +#define FE_CMPLEXADD32mrr 0xf80000010a00ee +#define FE_CMPLEXADD64mrr 0xf80000014a00ee +#define FE_CMPNLEXADD32mrr 0xf80000010a00ef +#define FE_CMPNLEXADD64mrr 0xf80000014a00ef +#define FE_AESENCWIDE128KLm 0x100000002200d8 +#define FE_AESDECWIDE128KLm 0x100000002201d8 +#define FE_AESENCWIDE256KLm 0x100000002202d8 +#define FE_AESDECWIDE256KLm 0x100000002203d8 +#define FE_AESENC128KLrm 0x380000002200dc +#define FE_LOADIWKEYrr 0x380000002200dc +#define FE_AESDEC128KLrm 0x380000002200dd +#define FE_AESENC256KLrm 0x380000002200de +#define FE_AESDEC256KLrm 0x380000002200df +#define FE_ENCODEKEY128rr 0x380000002200fa +#define FE_ENCODEKEY256rr 0x380000002200fb +#define FE_LKGSm 0x10000000110600 +#define FE_LKGSr 0x10000000110600 +#define FE_ERETU 0x800000021ca01 +#define FE_ERETS 0x800000011ca01 +#define FE_KANDBrrr 0xc0000001890041 +#define FE_KANDWrrr 0xc0000001810041 +#define FE_KANDDrrr 0xc0000001c90041 +#define FE_KANDQrrr 0xc0000001c10041 +#define FE_KANDNBrrr 0xc0000001890042 +#define FE_KANDNWrrr 0xc0000001810042 +#define FE_KANDNDrrr 0xc0000001c90042 +#define FE_KANDNQrrr 0xc0000001c10042 +#define FE_KNOTBrr 0x38000001090044 +#define FE_KNOTWrr 0x38000001010044 +#define FE_KNOTDrr 0x38000001490044 +#define FE_KNOTQrr 0x38000001410044 +#define FE_KORBrrr 0xc0000001890045 +#define FE_KORWrrr 0xc0000001810045 +#define FE_KORDrrr 0xc0000001c90045 +#define FE_KORQrrr 0xc0000001c10045 +#define FE_KXNORBrrr 0xc0000001890046 +#define FE_KXNORWrrr 0xc0000001810046 +#define FE_KXNORDrrr 0xc0000001c90046 +#define FE_KXNORQrrr 0xc0000001c10046 +#define FE_KXORBrrr 0xc0000001890047 +#define FE_KXORWrrr 0xc0000001810047 +#define FE_KXORDrrr 0xc0000001c90047 +#define FE_KXORQrrr 0xc0000001c10047 +#define FE_KADDBrrr 0xc000000189004a +#define FE_KADDWrrr 0xc000000181004a +#define FE_KADDDrrr 0xc0000001c9004a +#define FE_KADDQrrr 0xc0000001c1004a +#define FE_KUNPCKBWrrr 0xc000000189004b +#define FE_KUNPCKWDrrr 0xc000000181004b +#define FE_KUNPCKDQrrr 0xc0000001c1004b +#define FE_KORTESTBrr 0x38000001090098 +#define FE_KORTESTWrr 0x38000001010098 +#define FE_KORTESTDrr 0x38000001490098 +#define FE_KORTESTQrr 0x38000001410098 +#define FE_KMOVBrm 0x38000001090090 +#define FE_KMOVBrr 0x38000001090090 +#define FE_KMOVWrm 0x38000001010090 +#define FE_KMOVWrr 0x38000001010090 +#define FE_KMOVDrm 0x38000001490090 +#define FE_KMOVDrr 0x38000001490090 +#define FE_KMOVQrm 0x38000001410090 +#define FE_KMOVQrr 0x38000001410090 +#define FE_KMOVBmr 0x30000001090091 +#define FE_KMOVWmr 0x30000001010091 +#define FE_KMOVDmr 0x30000001490091 +#define FE_KMOVQmr 0x30000001410091 +#define FE_KTESTBrr 0x38000001090099 +#define FE_KTESTWrr 0x38000001010099 +#define FE_KTESTDrr 0x38000001490099 +#define FE_KTESTQrr 0x38000001410099 +#define FE_KSHIFTRBrri 0x508000010b0030 +#define FE_KSHIFTRWrri 0x508000014b0030 +#define FE_KSHIFTRDrri 0x508000010b0031 +#define FE_KSHIFTRQrri 0x508000014b0031 +#define FE_KSHIFTLBrri 0x508000010b0032 +#define FE_KSHIFTLWrri 0x508000014b0032 +#define FE_KSHIFTLDrri 0x508000010b0033 +#define FE_KSHIFTLQrri 0x508000014b0033 +#define FE_NOP 0x8000000000090 diff --git a/src/faenc.rs b/src/faenc.rs new file mode 100644 index 0000000..645461b --- /dev/null +++ b/src/faenc.rs @@ -0,0 +1,97 @@ +mod defs { +#![allow(non_upper_case_globals)] +#![allow(non_camel_case_types)] +#![allow(non_snake_case)] +#![allow(dead_code)] +include!(concat!(env!("OUT_DIR"), "/bindings.rs")); +} + +pub mod insts { +#![allow(non_upper_case_globals)] +#![allow(non_camel_case_types)] +#![allow(non_snake_case)] +#![allow(dead_code)] +include!(concat!(env!("OUT_DIR"), "/inst_bindings.rs")); +} + +pub use defs::{FeReg, FeOp, FE_ADDR32, FE_NOREG, FE_JMPL}; + +// this does not seem to be defined by bindgen on wasm? +#[cfg(target_arch = "wasm32")] +extern "C" { + pub fn fe_enc64_impl(buf: *mut *mut u8, mnem: u64, op0: FeOp, op1: FeOp, op2: FeOp, op3: FeOp) -> core::ffi::c_int; +} + +#[cfg(not(target_arch = "wasm32"))] +use defs::fe_enc64_impl; + +/*impl Into for FeReg { + fn into(self) -> FeOp { + self as FeOp + } +}*/ + +impl From for FeOp { + fn from(value: FeReg) -> Self { + value as FeOp + } +} + +pub fn fe_mem(base: Option, scale: u8, idx: Option, off: i32) -> FeOp { + let base = (base.map(|x| x as i64).unwrap_or(0) & 0xFFF) << 32; + let idx = (idx.map(|x| x as i64).unwrap_or(0) & 0xFFF) << 44; + let sc = ((scale & 0xF) as i64) << 56; + i64::MIN | base | idx | sc | (off as i64) & 0xFFFFFFFF +} + +pub fn fe_seg(seg: u64) -> u64 { + ((seg & 0x7) + 1) << 29 +} + +pub fn fe_mask(kreg: u64) -> u64 { + (kreg & 0x7) << 33 +} + +pub fn fe_maskz(kreg: u64) -> u64 { + ((kreg & 0x7) << 33) | 0x1000000000 +} + +pub unsafe fn fe_enc64_0(buf_ptr: *mut *mut u8, mnem: u64) -> Result<(), core::ffi::c_int> { + let res = fe_enc64_impl(buf_ptr, mnem, 0, 0, 0, 0); + match res { + 0 => Ok(()), + x => Err(x) + } +} + +pub unsafe fn fe_enc64_1(buf_ptr: *mut *mut u8, mnem: u64, op0: FeOp) -> Result<(), core::ffi::c_int> { + let res = fe_enc64_impl(buf_ptr, mnem, op0, 0, 0, 0); + match res { + 0 => Ok(()), + x => Err(x) + } +} + +pub unsafe fn fe_enc64_2(buf_ptr: *mut *mut u8, mnem: u64, op0: FeOp, op1: FeOp) -> Result<(), core::ffi::c_int> { + let res = fe_enc64_impl(buf_ptr, mnem, op0, op1, 0, 0); + match res { + 0 => Ok(()), + x => Err(x) + } +} + +pub unsafe fn fe_enc64_3(buf_ptr: *mut *mut u8, mnem: u64, op0: FeOp, op1: FeOp, op2: FeOp) -> Result<(), core::ffi::c_int> { + let res = fe_enc64_impl(buf_ptr, mnem, op0, op1, op2, 0); + match res { + 0 => Ok(()), + x => Err(x) + } +} + +pub unsafe fn fe_enc64_4(buf_ptr: *mut *mut u8, mnem: u64, op0: FeOp, op1: FeOp, op2: FeOp, op3: FeOp) -> Result<(), core::ffi::c_int> { + let res = fe_enc64_impl(buf_ptr, mnem, op0, op1, op2, op3); + match res { + 0 => Ok(()), + x => Err(x) + } +} \ No newline at end of file diff --git a/src/lib.rs b/src/lib.rs new file mode 100644 index 0000000..f9205be --- /dev/null +++ b/src/lib.rs @@ -0,0 +1,125 @@ +mod utils; + +use wasm_bindgen::prelude::*; + +// When the `wee_alloc` feature is enabled, use `wee_alloc` as the global +// allocator. +#[cfg(feature = "wee_alloc")] +#[global_allocator] +static ALLOC: wee_alloc::WeeAlloc = wee_alloc::WeeAlloc::INIT; + +#[wasm_bindgen] +extern { + fn alert(s: &str); +} + +mod faenc; +mod op_defs; + +use faenc::fe_enc64_1; +use faenc::FeReg; +use faenc::insts; + + +#[wasm_bindgen] +pub fn greet() { + let mut buf = [0u8; 16]; + unsafe { + let mut write_ptr = buf.as_mut_ptr(); + + fe_enc64_1(&mut write_ptr, insts::FE_INC32r, FeReg::AX.into()).unwrap(); + } + + alert(&format!("Hello, rust-as: {:X?}", buf)); +} + +enum Operand { + Mem(u8, FeReg, u8, FeReg, i32), // width, base, sc, idx, off + Reg(u8, FeReg), // width + Imm(i64), +} + +#[wasm_bindgen] +pub fn parse_string(asm: &str) { + let mut enc_vec = Vec::::new(); + enc_vec.resize(1024, 0); + + let mut err_str = None; + for line in asm.lines() { + let line = line.trim(); + // Remove comments + let line = match line.find(|c: char| c == '#' || c == ';') { + None => line, + Some(idx) => &line[..idx] + }; + let line = match line.find("//") { + None => line, + Some(idx) => &line[..idx] + }; + if line.is_empty() { + continue; + } + + let line = line.trim(); + let (mnem, ops_str) = match line.find(' ') { + None => { + // no operands instruction + err_str = Some("Instruction without op not supported".to_owned()); + break; + }, + Some(idx) => { + (&line[..idx], &line[idx+1..]) + } + }; + + let op_strs: Vec<&str> = ops_str.split(',').map(|op| op.trim()).collect(); + let mut ops = Vec::new(); + + for op_str in op_strs { + if let Some(first_space) = op_str.find(' ') { + let (first, op_str) = op_str.split_at(first_space); + let first = first.trim(); + if let Some(second_space) = op_str.find(' ') { + let (second, op_str) = op_str.split_at(second_space); + + if second.trim().eq_ignore_ascii_case("ptr") { + let mut width = 0; + if first.eq_ignore_ascii_case("byte") { + width = 1; + } + if first.eq_ignore_ascii_case("word") { + width = 2; + } + if first.eq_ignore_ascii_case("dword") { + width = 4; + } + if first.eq_ignore_ascii_case("qword") { + width = 8; + } + + if width != 0 { + // parse mem operand + + + } + } + } + } + } + + if err_str.is_some() { + break; + } + } +} + + +fn parse_mem_op_inner(op_str: &str) -> Result<(FeReg, u8, FeReg, i32), String> { + let op_str = op_str.trim(); + if op_str.is_empty() || op_str.chars().nth(0).unwrap() != '[' || op_str.chars().nth_back(0).unwrap() != ']' { + return Err("Expected memory operand".to_owned()); + } + + + todo!("") +} \ No newline at end of file diff --git a/src/op_defs.rs b/src/op_defs.rs new file mode 100644 index 0000000..385f030 --- /dev/null +++ b/src/op_defs.rs @@ -0,0 +1,80 @@ +// The lookup table for mnemonics is divided into multiple hashmaps +// There is one each for the operand combinations: +// mem, reg, imm, +// reg+reg, reg+mem, reg+imm, mem+reg, mem+imm, +// reg+reg+reg, reg+reg+mem, reg+reg+imm, reg+mem+reg, reg+mem+imm, mem+reg+reg, mem+reg+imm +// reg+reg+reg+reg, reg+reg+reg+imm, reg+reg+mem+imm, reg+reg+mem+reg + +use std::num::NonZeroU64; +use phf::phf_map; + +use crate::faenc::FeOp; + +struct OpDef { + byte_op: Option, + word_op: Option, + dword_op: Option, + qword_op: Option, + // TODO: extra lookup for SSE+ ops? + op_128: Option, + op_256: Option, + op_512: Option, +} + +impl OpDef { + const fn d4(byte_op: u64, word_op: u64, dword_op: u64, qword_op: u64) -> Self { + unsafe { + let byte_op = if byte_op == 0 { + None + } else { + Some(NonZeroU64::new_unchecked(byte_op)) + }; + let word_op = if word_op == 0 { + None + } else { + Some(NonZeroU64::new_unchecked(word_op)) + }; + let dword_op = if dword_op == 0 { + None + } else { + Some(NonZeroU64::new_unchecked(dword_op)) + }; + let qword_op = if qword_op == 0 { + None + } else { + Some(NonZeroU64::new_unchecked(qword_op)) + }; + Self { + byte_op, + word_op, + dword_op, + qword_op, + op_128: None, + op_256: None, + op_512: None + } + } + } +} + +// No checks done by default +struct OpDefMem { + def: OpDef, + encoding_fn: Option bool>, +} + +impl OpDefMem { + const fn d4(encoding_fn: Option bool>, byte_op: u64, word_op: u64, dword_op: u64, qword_op: u64) -> Self { + Self { + def: OpDef::d4(byte_op, word_op, dword_op, qword_op), + encoding_fn + } + } +} + +use crate::faenc::insts::*; + +static MAP_MEM: phf::Map<&'static str, OpDefMem> = phf_map! { + "mul" => OpDefMem::d4(None, FE_MUL8m, FE_MUL16m, FE_MUL32m, FE_MUL64m), + "push" => OpDefMem::d4(None, 0, FE_PUSH16m, 0, FE_PUSHm), +}; \ No newline at end of file diff --git a/src/utils.rs b/src/utils.rs new file mode 100644 index 0000000..b1d7929 --- /dev/null +++ b/src/utils.rs @@ -0,0 +1,10 @@ +pub fn set_panic_hook() { + // When the `console_error_panic_hook` feature is enabled, we can call the + // `set_panic_hook` function at least once during initialization, and then + // we will get better error messages if our code ever panics. + // + // For more details see + // https://github.com/rustwasm/console_error_panic_hook#readme + #[cfg(feature = "console_error_panic_hook")] + console_error_panic_hook::set_once(); +} diff --git a/tests/web.rs b/tests/web.rs new file mode 100644 index 0000000..de5c1da --- /dev/null +++ b/tests/web.rs @@ -0,0 +1,13 @@ +//! Test suite for the Web and headless browsers. + +#![cfg(target_arch = "wasm32")] + +extern crate wasm_bindgen_test; +use wasm_bindgen_test::*; + +wasm_bindgen_test_configure!(run_in_browser); + +#[wasm_bindgen_test] +fn pass() { + assert_eq!(1 + 1, 2); +} diff --git a/www/test.html b/www/test.html new file mode 100644 index 0000000..83beb60 --- /dev/null +++ b/www/test.html @@ -0,0 +1,13 @@ + + + + + + \ No newline at end of file