Chris Fallin b3dc2b25a5 Alloc spillsets for whole vreg, not just spilled LRs. This is a prerequisite to allowing a "clean" value to remain in spillslot while also in reg and avoiding the re-spill. It should also reduce stack-to-stack moves (though they can still come from progmoves).

2021-05-25 18:19:25 -07:00

..

fuzzing

Properly handle prog-moves with fixed srcs or dests

2021-05-09 13:35:38 -07:00

ion

Alloc spillsets for whole vreg, not just spilled LRs. This is a prerequisite to allowing a "clean" value to remain in spillslot while also in reg and avoiding the re-spill. It should also reduce stack-to-stack moves (though they can still come from progmoves).

2021-05-25 18:19:25 -07:00

bitvec.rs

Fuzzbugfix: actually do need eager liveness computation; must uphold invariant that all earlier-in-postorder blocks have full livein sets.

2021-05-06 23:29:59 -07:00

cfg.rs

Loop depth instead of hot/cold, with fast O(n) loop-depth computation. Use this to compute use weights.

2021-05-24 22:09:41 -07:00

checker.rs

WIP: Handle moves between realregs (pregs) and vregs somewhat specially, by converting into operand constraints

2021-05-20 19:53:19 -07:00

domtree.rs

Initial public commit of regalloc2.

2021-04-13 17:40:12 -07:00

index.rs

Optionally show annotations in final allocation/program dump based on RegallocOptions flag

2021-05-19 16:36:36 -07:00

lib.rs

WIP: Handle moves between realregs (pregs) and vregs somewhat specially, by converting into operand constraints

2021-05-20 19:53:19 -07:00

moves.rs

Improve prog-move handling: no use/def records, just directly connect the LRs.

2021-05-11 23:59:12 -07:00

postorder.rs

Changes from review comments.

2021-04-18 13:12:33 -07:00

ssa.rs

Support mod (modify) operands, for better efficiency with regalloc.rs/Cranelift shim.

2021-05-07 19:48:34 -07:00