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Amanieu d'Antras
2021-09-14 13:12:52 +01:00
parent 35ed2109b1
commit 9e2ab3d5f7
1 changed files with 10 additions and 3 deletions
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13
src/lib.rs
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@@ -60,8 +60,8 @@ pub enum RegClass {
/// The value returned by `index()`, in contrast, is in a single index /// The value returned by `index()`, in contrast, is in a single index
/// space shared by all classes, in order to enable uniform reasoning /// space shared by all classes, in order to enable uniform reasoning
/// about physical registers. This is done by putting the class bit at /// about physical registers. This is done by putting the class bit at
/// the MSB, or equivalently, declaring that indices 0..63 are the 64 /// the MSB, or equivalently, declaring that indices 0..=63 are the 64
/// integer registers and indices 64..127 are the 64 float registers. /// integer registers and indices 64..=127 are the 64 float registers.
#[derive(Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash)] #[derive(Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash)]
pub struct PReg { pub struct PReg {
hw_enc: u8, hw_enc: u8,
@@ -383,7 +383,6 @@ pub enum OperandPos {
/// that the conflict (overlap) is properly accounted for. See /// that the conflict (overlap) is properly accounted for. See
/// comments on the constructors below for more. /// comments on the constructors below for more.
#[derive(Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash)] #[derive(Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash)]
//#[repr(packed)]
pub struct Operand { pub struct Operand {
/// Bit-pack into 32 bits. /// Bit-pack into 32 bits.
/// ///
@@ -392,6 +391,14 @@ pub struct Operand {
/// where `constraint` is an `OperandConstraint`, `kind` is an /// where `constraint` is an `OperandConstraint`, `kind` is an
/// `OperandKind`, `pos` is an `OperandPos`, `class` is a /// `OperandKind`, `pos` is an `OperandPos`, `class` is a
/// `RegClass`, and `vreg` is a vreg index. /// `RegClass`, and `vreg` is a vreg index.
///
/// The constraints are encoded as follows:
/// - 1xxxxxx => FixedReg(preg)
/// - 01xxxxx => Reuse(index)
/// - 0000000 => Any
/// - 0000001 => Reg
/// - 0000010 => Stack
/// - _ => Unused for now
bits: u32, bits: u32,
} }