From 2f856435f413819ad1af05f62bddd08615c18d5e Mon Sep 17 00:00:00 2001
From: Chris Fallin <chris@cfallin.org>
Date: Thu, 12 Aug 2021 14:08:10 -0700
Subject: [PATCH] Review feedback.

---
 src/bitvec.rs    | 15 ++++++++-------
 src/ion/mod.rs   |  2 +-
 src/ion/moves.rs |  8 ++++----
 src/lib.rs       | 14 ++++++++------
 4 files changed, 21 insertions(+), 18 deletions(-)

diff --git a/src/bitvec.rs b/src/bitvec.rs
index 5c2cc2f..bb6665b 100644
--- a/src/bitvec.rs
+++ b/src/bitvec.rs
@@ -265,13 +265,14 @@ pub struct SetBitsIter(u64);
 impl Iterator for SetBitsIter {
     type Item = usize;
     fn next(&mut self) -> Option<usize> {
-        if self.0 == 0 {
-            None
-        } else {
-            let bitidx = self.0.trailing_zeros();
-            self.0 &= !(1 << bitidx);
-            Some(bitidx as usize)
-        }
+        // Build an `Option<NonZeroU64>` so that on the nonzero path,
+        // the compiler can optimize the trailing-zeroes operator
+        // using that knowledge.
+        std::num::NonZeroU64::new(self.0).map(|nz| {
+            let bitidx = nz.trailing_zeros();
+            self.0 &= self.0 - 1; // clear highest set bit
+            bitidx as usize
+        })
     }
 }
 
diff --git a/src/ion/mod.rs b/src/ion/mod.rs
index abbed9e..b224f34 100644
--- a/src/ion/mod.rs
+++ b/src/ion/mod.rs
@@ -96,7 +96,7 @@ impl<'a, F: Function> Env<'a, F> {
         self.compute_liveness()?;
         self.merge_vreg_bundles();
         self.queue_bundles();
-        if log::log_enabled!(log::Level::Debug) {
+        if log::log_enabled!(log::Level::Trace) {
             self.dump_state();
         }
         Ok(())
diff --git a/src/ion/moves.rs b/src/ion/moves.rs
index 351c0ca..4564890 100644
--- a/src/ion/moves.rs
+++ b/src/ion/moves.rs
@@ -411,9 +411,9 @@ impl<'a, F: Function> Env<'a, F> {
                                     from_block.index(),
                                     alloc,
                                 );
-                                #[cfg(debug)]
+                                #[cfg(debug_assertions)]
                                 {
-                                    if log::log_enabled!(log::Level::Debug) {
+                                    if log::log_enabled!(log::Level::Trace) {
                                         self.annotate(
                                             self.cfginfo.block_entry[block.index()],
                                             format!(
@@ -772,9 +772,9 @@ impl<'a, F: Function> Env<'a, F> {
                         input_alloc
                     );
                     if input_alloc != output_alloc {
-                        #[cfg(debug)]
+                        #[cfg(debug_assertions)]
                         {
-                            if log::log_enabled!(log::Level::Debug) {
+                            if log::log_enabled!(log::Level::Trace) {
                                 self.annotate(
                                     ProgPoint::before(inst),
                                     format!(
diff --git a/src/lib.rs b/src/lib.rs
index 3003081..9e634b3 100644
--- a/src/lib.rs
+++ b/src/lib.rs
@@ -47,15 +47,16 @@ impl PReg {
 
     /// Create a new PReg. The `hw_enc` range is 6 bits.
     #[inline(always)]
-    pub fn new(hw_enc: usize, class: RegClass) -> Self {
-        assert!(hw_enc <= Self::MAX);
+    pub const fn new(hw_enc: usize, class: RegClass) -> Self {
         PReg(hw_enc as u8, class)
     }
 
     /// The physical register number, as encoded by the ISA for the particular register class.
     #[inline(always)]
     pub fn hw_enc(self) -> usize {
-        self.0 as usize
+        let hw_enc = self.0 as usize;
+        debug_assert!(hw_enc <= Self::MAX);
+        hw_enc
     }
 
     /// The register class.
@@ -121,14 +122,15 @@ impl VReg {
     pub const MAX: usize = (1 << Self::MAX_BITS) - 1;
 
     #[inline(always)]
-    pub fn new(virt_reg: usize, class: RegClass) -> Self {
-        assert!(virt_reg <= Self::MAX);
+    pub const fn new(virt_reg: usize, class: RegClass) -> Self {
         VReg(((virt_reg as u32) << 1) | (class as u8 as u32))
     }
 
     #[inline(always)]
     pub fn vreg(self) -> usize {
-        (self.0 >> 1) as usize
+        let vreg = (self.0 >> 1) as usize;
+        debug_assert!(vreg <= Self::MAX);
+        vreg
     }
 
     #[inline(always)]