WIP: Handle moves between realregs (pregs) and vregs somewhat specially, by converting into operand constraints

Still has a fuzzbug in interaction between R->R and V->R moves. Will
likely rework to make pinned-vreg handling more general but want to save
a checkpoint here; idea for rework:
- set allocs immediately if an Operand is a pinned vreg;
- reserve preg ranges;
- then, in rest of liveness computation / LR construction, convert
  pinned-vregs to operands with constraints, but otherwise do not
  special-case as we do in this commit.

src/lib.rs

@@ -906,6 +906,9 @@ pub enum Edit {
         vregs: Vec<VReg>,
         allocs: Vec<Allocation>,
     },
+    /// Define a particular Allocation to contain a particular VReg. Useful
+    /// for the checker.
+    DefAlloc { alloc: Allocation, vreg: VReg },
 }
 
 /// A machine envrionment tells the register allocator which registers