33
src/lib.rs
33
src/lib.rs
@@ -426,14 +426,13 @@ impl std::fmt::Display for OperandConstraint {
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}
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}
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/// The "kind" of the operand: whether it reads a vreg (Use), writes a
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/// vreg (Def), or reads and then writes (Mod, for "modify").
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/// The "kind" of the operand: whether it reads a vreg (Use) or writes
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/// a vreg (Def).
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#[derive(Clone, Copy, Debug, PartialEq, Eq)]
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#[cfg_attr(feature = "enable-serde", derive(Serialize, Deserialize))]
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pub enum OperandKind {
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Def = 0,
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Mod = 1,
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Use = 2,
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Use = 1,
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}
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/// The "position" of the operand: where it has its read/write
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@@ -488,7 +487,7 @@ pub enum OperandPos {
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pub struct Operand {
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/// Bit-pack into 32 bits.
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///
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/// constraint:7 kind:2 pos:1 class:1 vreg:21
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/// constraint:7 kind:1 pos:1 class:2 vreg:21
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///
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/// where `constraint` is an `OperandConstraint`, `kind` is an
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/// `OperandKind`, `pos` is an `OperandPos`, `class` is a
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@@ -532,8 +531,8 @@ impl Operand {
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Operand {
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bits: vreg.vreg() as u32
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| (class_field << 21)
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| (pos_field << 22)
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| (kind_field << 23)
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| (pos_field << 23)
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| (kind_field << 24)
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| (constraint_field << 25),
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}
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}
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@@ -719,7 +718,7 @@ impl Operand {
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/// Get the register class used by this operand.
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#[inline(always)]
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pub fn class(self) -> RegClass {
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let class_field = (self.bits >> 21) & 1;
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let class_field = (self.bits >> 21) & 3;
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match class_field {
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0 => RegClass::Int,
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1 => RegClass::Float,
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@@ -727,15 +726,14 @@ impl Operand {
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}
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}
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/// Get the "kind" of this operand: a definition (write), a use
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/// (read), or a "mod" / modify (a read followed by a write).
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/// Get the "kind" of this operand: a definition (write) or a use
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/// (read).
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#[inline(always)]
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pub fn kind(self) -> OperandKind {
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let kind_field = (self.bits >> 23) & 3;
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let kind_field = (self.bits >> 24) & 1;
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match kind_field {
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0 => OperandKind::Def,
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1 => OperandKind::Mod,
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2 => OperandKind::Use,
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1 => OperandKind::Use,
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_ => unreachable!(),
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}
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}
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@@ -746,7 +744,7 @@ impl Operand {
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/// at "after", though there are cases where this is not true.
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#[inline(always)]
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pub fn pos(self) -> OperandPos {
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let pos_field = (self.bits >> 22) & 1;
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let pos_field = (self.bits >> 23) & 1;
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match pos_field {
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0 => OperandPos::Early,
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1 => OperandPos::Late,
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@@ -808,8 +806,7 @@ impl std::fmt::Debug for Operand {
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impl std::fmt::Display for Operand {
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fn fmt(&self, f: &mut std::fmt::Formatter) -> std::fmt::Result {
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match (self.kind(), self.pos()) {
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(OperandKind::Def, OperandPos::Late)
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| (OperandKind::Mod | OperandKind::Use, OperandPos::Early) => {
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(OperandKind::Def, OperandPos::Late) | (OperandKind::Use, OperandPos::Early) => {
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write!(f, "{:?}", self.kind())?;
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}
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_ => {
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@@ -1058,8 +1055,8 @@ pub trait Function {
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/// it in a given PReg chosen by the client prior to regalloc.
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///
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/// Every register written by an instruction must either
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/// correspond to (be assigned to) an Operand of kind `Def` or
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/// `Mod`, or else must be a "clobber".
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/// correspond to (be assigned to) an Operand of kind `Def`, or
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/// else must be a "clobber".
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///
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/// This can be used to, for example, describe ABI-specified
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/// registers that are not preserved by a call instruction, or
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