53ca6a2f23
This was previously needed to distinguish VZEROALL and VZEROUPPER. As mandatory VEX.L is now handled properly, there is no need to export this encoding detail any longer.
632 lines
19 KiB
C
632 lines
19 KiB
C
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#include <stddef.h>
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#include <stdint.h>
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#include <fadec.h>
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#if defined(ARCH_X86_64) && __SIZEOF_POINTER__ < 8
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#error "Decoding x86-64 requires a 64-bit architecture"
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#endif
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#define LIKELY(x) __builtin_expect((x), 1)
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#define UNLIKELY(x) __builtin_expect((x), 0)
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#define FD_DECODE_TABLE_DATA
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static const uint8_t _decode_table[] = {
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#include <decode-table.inc>
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};
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#undef FD_DECODE_TABLE_DATA
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// Defines FD_TABLE_OFFSET_32 and FD_TABLE_OFFSET_64, if available
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#define FD_DECODE_TABLE_DEFINES
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#include <decode-table.inc>
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#undef FD_DECODE_TABLE_DEFINES
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enum DecodeMode {
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DECODE_64 = 0,
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DECODE_32 = 1,
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};
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typedef enum DecodeMode DecodeMode;
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#define ENTRY_NONE 0
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#define ENTRY_INSTR 1
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#define ENTRY_TABLE256 2
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#define ENTRY_TABLE8 3
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#define ENTRY_TABLE72 4
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#define ENTRY_TABLE_PREFIX 5
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#define ENTRY_TABLE_VEX 6
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#define ENTRY_MASK 7
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#define ENTRY_IS_TABLE(kind) ((kind) >= ENTRY_TABLE256)
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#define ENTRY_UNPACK(table,kind,decode_table,entry) do { \
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uint16_t entry_copy = entry; \
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table = (uint16_t*) &(decode_table)[entry_copy & ~7]; \
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kind = entry_copy & ENTRY_MASK; \
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} while (0)
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#define INSTR_ENC_ADDR 0x08
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#define INSTR_ENC_IMM 0x10
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#define INSTR_ENC_MODRM 0x80
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#define INSTR_ENC_MODRM_BOTH 0x40
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#define INSTR_ENC_FLIP 0x20
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#define INSTR_ENC_OPCODE 0x40
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#define INSTR_ENC_IMPLICIT_REG 0x04
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#define LOAD_LE_1(buf) (((size_t) ((uint8_t*) buf)[0]))
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#define LOAD_LE_2(buf) (((size_t) ((uint8_t*) buf)[0]) | \
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((size_t) ((uint8_t*) buf)[1] << 8))
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#define LOAD_LE_4(buf) (((size_t) ((uint8_t*) buf)[0]) | \
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((size_t) ((uint8_t*) buf)[1] << 8) | \
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((size_t) ((uint8_t*) buf)[2] << 16) | \
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((size_t) ((uint8_t*) buf)[3] << 24))
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#if defined(ARCH_X86_64)
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#define LOAD_LE_8(buf) (((size_t) ((uint8_t*) buf)[0]) | \
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((size_t) ((uint8_t*) buf)[1] << 8) | \
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((size_t) ((uint8_t*) buf)[2] << 16) | \
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((size_t) ((uint8_t*) buf)[3] << 24) | \
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((size_t) ((uint8_t*) buf)[4] << 32) | \
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((size_t) ((uint8_t*) buf)[5] << 40) | \
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((size_t) ((uint8_t*) buf)[6] << 48) | \
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((size_t) ((uint8_t*) buf)[7] << 56))
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#endif
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enum PrefixSet
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{
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PREFIX_LOCK = FD_FLAG_LOCK,
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PREFIX_REP = FD_FLAG_REP,
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PREFIX_REPNZ = FD_FLAG_REPNZ,
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PREFIX_REX = FD_FLAG_REX,
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PREFIX_OPSZ = 1 << 13,
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PREFIX_ADDRSZ = 1 << 14,
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PREFIX_REXB = 1 << 15,
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PREFIX_REXX = 1 << 16,
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PREFIX_REXR = 1 << 17,
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PREFIX_REXW = 1 << 18,
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PREFIX_VEXL = 1 << 19,
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PREFIX_VEX = 1 << 20,
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};
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typedef enum PrefixSet PrefixSet;
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static
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int
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decode_prefixes(const uint8_t* buffer, int len, DecodeMode mode,
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PrefixSet* out_prefixes, uint8_t* out_mandatory,
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uint8_t* out_segment, uint8_t* out_vex_operand,
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int* out_opcode_escape)
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{
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int off = 0;
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PrefixSet prefixes = 0;
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uint8_t rep = 0;
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*out_mandatory = 0;
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*out_segment = FD_REG_NONE;
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*out_opcode_escape = -1;
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while (LIKELY(off < len))
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{
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uint8_t prefix = buffer[off];
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switch (prefix)
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{
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default: goto out;
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// From segment overrides, the last one wins.
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case 0x26: *out_segment = FD_REG_ES; off++; break;
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case 0x2e: *out_segment = FD_REG_CS; off++; break;
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case 0x3e: *out_segment = FD_REG_DS; off++; break;
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case 0x64: *out_segment = FD_REG_FS; off++; break;
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case 0x65: *out_segment = FD_REG_GS; off++; break;
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case 0x67: prefixes |= PREFIX_ADDRSZ; off++; break;
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case 0xf0: prefixes |= PREFIX_LOCK; off++; break;
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case 0x66: prefixes |= PREFIX_OPSZ; off++; break;
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// From REP/REPE and REPNZ, the last one wins; and for mandatory
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// prefixes they have a higher priority than 66h (handled below).
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case 0xf3: rep = PREFIX_REP; *out_mandatory = 2; off++; break;
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case 0xf2: rep = PREFIX_REPNZ; *out_mandatory = 3; off++; break;
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#if defined(ARCH_X86_64)
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case 0x40: case 0x41: case 0x42: case 0x43: case 0x44: case 0x45:
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case 0x46: case 0x47: case 0x48: case 0x49: case 0x4a: case 0x4b:
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case 0x4c: case 0x4d: case 0x4e: case 0x4f:
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if (mode == DECODE_64)
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{
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prefixes |= PREFIX_REX;
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prefixes |= prefix & 0x1 ? PREFIX_REXB : 0;
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prefixes |= prefix & 0x2 ? PREFIX_REXX : 0;
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prefixes |= prefix & 0x4 ? PREFIX_REXR : 0;
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prefixes |= prefix & 0x8 ? PREFIX_REXW : 0;
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off++;
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}
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// If in 64-bit mode, the REX prefix is always the last prefix. In
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// 32-bit mode these are regular opcodes, so exit without consuming.
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goto out;
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#endif
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case 0xc4: case 0xc5: // VEX
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if (UNLIKELY(off + 1 >= len))
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return -1;
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uint8_t byte = buffer[off + 1];
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if (mode == DECODE_32 && (byte & 0xc0) != 0xc0)
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goto out;
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prefixes |= PREFIX_VEX;
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prefixes |= byte & 0x80 ? 0 : PREFIX_REXR;
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if (prefix == 0xc4) // 3-byte VEX
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{
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prefixes |= byte & 0x80 ? 0 : PREFIX_REXR;
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prefixes |= byte & 0x40 ? 0 : PREFIX_REXX;
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// SDM Vol 2A 2-15 (Dec. 2016): Ignored in 32-bit mode
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prefixes |= mode == DECODE_64 || (byte & 0x20) ? 0 : PREFIX_REXB;
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*out_opcode_escape = (byte & 0x1f);
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// Load third byte of VEX prefix
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if (UNLIKELY(off + 2 >= len))
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return -1;
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byte = buffer[off + 2];
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// SDM Vol 2A 2-16 (Dec. 2016) says that:
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// - "In 32-bit modes, VEX.W is silently ignored."
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// - VEX.W either replaces REX.W, is don't care or is reserved.
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// This is actually incorrect, there are instructions that
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// use VEX.W as an opcode extension even in 32-bit mode.
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prefixes |= byte & 0x80 ? PREFIX_REXW : 0;
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}
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else // 2-byte VEX
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*out_opcode_escape = 1;
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prefixes |= byte & 0x04 ? PREFIX_VEXL : 0;
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*out_mandatory = byte & 0x03;
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*out_vex_operand = ((byte & 0x78) >> 3) ^ 0xf;
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// VEX prefix is always the last prefix.
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off += prefix == 0xc4 ? 3 : 2;
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goto out;
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}
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}
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out:
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// If there is no REP/REPNZ prefix and implied opcode extension from a VEX
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// prefix, offer 66h as mandatory prefix. If there is a REP prefix, then the
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// 66h prefix is ignored when evaluating mandatory prefixes.
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if (*out_mandatory == 0 && (prefixes & PREFIX_OPSZ))
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*out_mandatory = 1;
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*out_prefixes = prefixes | rep;
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return off;
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}
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static
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int
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decode_modrm(const uint8_t* buffer, int len, DecodeMode mode, FdInstr* instr,
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PrefixSet prefixes, FdOp* out_o1, FdOp* out_o2)
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{
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int off = 0;
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if (UNLIKELY(off >= len))
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{
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return -1;
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}
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uint8_t modrm = buffer[off++];
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uint8_t mod = (modrm & 0xc0) >> 6;
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uint8_t mod_reg = (modrm & 0x38) >> 3;
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uint8_t rm = modrm & 0x07;
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// Operand 2 may be NULL when reg field is used as opcode extension
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if (out_o2)
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{
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uint8_t reg_idx = mod_reg;
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#if defined(ARCH_X86_64)
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reg_idx += prefixes & PREFIX_REXR ? 8 : 0;
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#endif
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out_o2->type = FD_OT_REG;
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out_o2->reg = reg_idx;
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}
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if (mod == 3)
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{
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uint8_t reg_idx = rm;
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#if defined(ARCH_X86_64)
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reg_idx += prefixes & PREFIX_REXB ? 8 : 0;
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#endif
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out_o1->type = FD_OT_REG;
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out_o1->reg = reg_idx;
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return off;
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}
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// SIB byte
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uint8_t scale = 0;
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uint8_t idx = 4;
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uint8_t base = rm;
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if (rm == 4)
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{
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if (UNLIKELY(off >= len))
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return -1;
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uint8_t sib = buffer[off++];
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scale = (sib & 0xc0) >> 6;
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idx = (sib & 0x38) >> 3;
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#if defined(ARCH_X86_64)
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idx += prefixes & PREFIX_REXX ? 8 : 0;
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#endif
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base = sib & 0x07;
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}
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out_o1->type = FD_OT_MEM;
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instr->idx_scale = scale;
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instr->idx_reg = idx == 4 ? FD_REG_NONE : idx;
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// RIP-relative addressing only if SIB-byte is absent
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if (mod == 0 && rm == 5 && mode == DECODE_64)
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out_o1->reg = FD_REG_IP;
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else if (mod == 0 && base == 5)
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out_o1->reg = FD_REG_NONE;
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else
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out_o1->reg = base + (prefixes & PREFIX_REXB ? 8 : 0);
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if (mod == 1)
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{
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if (UNLIKELY(off + 1 > len))
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return -1;
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instr->disp = (int8_t) LOAD_LE_1(&buffer[off]);
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off += 1;
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}
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else if (mod == 2 || (mod == 0 && base == 5))
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{
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if (UNLIKELY(off + 4 > len))
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return -1;
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instr->disp = (int32_t) LOAD_LE_4(&buffer[off]);
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off += 4;
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}
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else
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{
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instr->disp = 0;
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}
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return off;
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}
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struct InstrDesc
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{
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uint16_t type;
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uint8_t operand_indices;
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uint8_t operand_sizes;
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uint8_t immediate;
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uint8_t gp_size_8 : 1;
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uint8_t gp_size_def64 : 1;
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uint8_t gp_instr_width : 1;
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uint8_t gp_fixed_operand_size : 3;
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uint8_t lock : 1;
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} __attribute__((packed));
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#define DESC_HAS_MODRM(desc) (((desc)->operand_indices & (3 << 0)) != 0)
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#define DESC_MODRM_IDX(desc) ((((desc)->operand_indices >> 0) & 3) ^ 3)
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#define DESC_HAS_MODREG(desc) (((desc)->operand_indices & (3 << 2)) != 0)
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#define DESC_MODREG_IDX(desc) ((((desc)->operand_indices >> 2) & 3) ^ 3)
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#define DESC_HAS_VEXREG(desc) (((desc)->operand_indices & (3 << 4)) != 0)
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#define DESC_VEXREG_IDX(desc) ((((desc)->operand_indices >> 4) & 3) ^ 3)
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#define DESC_HAS_IMPLICIT(desc) (((desc)->operand_indices & (3 << 6)) != 0)
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#define DESC_IMPLICIT_IDX(desc) ((((desc)->operand_indices >> 6) & 3) ^ 3)
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#define DESC_IMM_CONTROL(desc) (((desc)->immediate >> 4) & 0x7)
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#define DESC_IMM_IDX(desc) (((desc)->immediate & 3) ^ 3)
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#define DESC_IMM_BYTE(desc) (((desc)->immediate >> 7) & 1)
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int
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fd_decode(const uint8_t* buffer, size_t len_sz, int mode_int, uintptr_t address,
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FdInstr* instr)
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{
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const uint16_t* table = NULL;
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int len = len_sz > 15 ? 15 : len_sz;
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DecodeMode mode = mode_int == 32 ? DECODE_32 :
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mode_int == 64 ? DECODE_64 : -1;
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// Ensure that we can actually handle the decode request
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#if defined(ARCH_386)
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if (mode == DECODE_32)
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table = (uint16_t*) &_decode_table[FD_TABLE_OFFSET_32];
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#endif
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#if defined(ARCH_X86_64)
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if (mode == DECODE_64)
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table = (uint16_t*) &_decode_table[FD_TABLE_OFFSET_64];
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#endif
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if (UNLIKELY(table == NULL))
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return -2;
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int retval;
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int off = 0;
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uint8_t vex_operand = 0;
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uint8_t mandatory_prefix;
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int opcode_escape;
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PrefixSet prefixes = 0;
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retval = decode_prefixes(buffer + off, len - off, mode, &prefixes,
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&mandatory_prefix, &instr->segment, &vex_operand,
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&opcode_escape);
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if (UNLIKELY(retval < 0 || off + retval >= len))
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{
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return -1;
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}
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off += retval;
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uint32_t kind = ENTRY_TABLE256;
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// "Legacy" walk through table and escape opcodes
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if (LIKELY(opcode_escape < 0))
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while (kind == ENTRY_TABLE256 && LIKELY(off < len))
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ENTRY_UNPACK(table, kind, _decode_table, table[buffer[off++]]);
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// VEX/EVEX compact escapes; the prefix precedes the single opcode byte
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else if (opcode_escape == 1 || opcode_escape == 2 || opcode_escape == 3)
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{
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ENTRY_UNPACK(table, kind, _decode_table, table[0x0F]);
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if (opcode_escape == 2)
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ENTRY_UNPACK(table, kind, _decode_table, table[0x38]);
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if (opcode_escape == 3)
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ENTRY_UNPACK(table, kind, _decode_table, table[0x3A]);
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if (LIKELY(off < len))
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ENTRY_UNPACK(table, kind, _decode_table, table[buffer[off++]]);
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}
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else
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return -1;
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// Then, walk through ModR/M-encoded opcode extensions.
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if ((kind == ENTRY_TABLE8 || kind == ENTRY_TABLE72) && LIKELY(off < len))
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{
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uint16_t entry = 0;
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if (kind == ENTRY_TABLE72 && (buffer[off] & 0xc0) == 0xc0)
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{
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entry = table[buffer[off] - 0xb8];
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if ((entry & ENTRY_MASK) != ENTRY_NONE)
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off++;
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else
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entry = table[(buffer[off] >> 3) & 7];
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}
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else
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entry = table[(buffer[off] >> 3) & 7];
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ENTRY_UNPACK(table, kind, _decode_table, entry);
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}
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// Handle mandatory prefixes (which behave like an opcode ext.).
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if (kind == ENTRY_TABLE_PREFIX)
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{
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uint8_t index = mandatory_prefix;
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index |= prefixes & PREFIX_VEX ? (1 << 2) : 0;
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// If a prefix is mandatory and used as opcode extension, it has no
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// further effect on the instruction. This is especially important
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// for the 0x66 prefix, which could otherwise override the operand
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// size of general purpose registers.
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prefixes &= ~(PREFIX_OPSZ | PREFIX_REPNZ | PREFIX_REP);
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ENTRY_UNPACK(table, kind, _decode_table, table[index]);
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}
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// For VEX prefix, we have to distinguish between VEX.W and VEX.L which may
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// be part of the opcode.
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if (kind == ENTRY_TABLE_VEX)
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{
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uint8_t index = 0;
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index |= prefixes & PREFIX_REXW ? (1 << 0) : 0;
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index |= prefixes & PREFIX_VEXL ? (1 << 1) : 0;
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ENTRY_UNPACK(table, kind, _decode_table, table[index]);
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}
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if (UNLIKELY(kind != ENTRY_INSTR))
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{
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return -1;
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}
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struct InstrDesc* desc = (struct InstrDesc*) table;
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instr->type = desc->type;
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instr->flags = prefixes & 0x7f;
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if (mode == DECODE_64)
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instr->flags |= FD_FLAG_64;
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instr->address = address;
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uint8_t op_size = 0;
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if (desc->gp_size_8)
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op_size = 1;
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else if (mode == DECODE_64 && (prefixes & PREFIX_REXW))
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op_size = 8;
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else if (prefixes & PREFIX_OPSZ)
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op_size = 2;
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else if (mode == DECODE_64 && desc->gp_size_def64)
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op_size = 8;
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else
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op_size = 4;
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instr->operandsz = desc->gp_instr_width ? op_size : 0;
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uint8_t vec_size = 16;
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if (prefixes & PREFIX_VEXL)
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{
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vec_size = 32;
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}
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// Compute address size.
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uint8_t addr_size = mode == DECODE_64 ? 8 : 4;
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if (prefixes & PREFIX_ADDRSZ)
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addr_size >>= 1;
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instr->addrsz = addr_size;
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uint8_t operand_sizes[4] = {
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0, 1 << desc->gp_fixed_operand_size, op_size, vec_size
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};
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__builtin_memset(instr->operands, 0, sizeof(instr->operands));
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for (int i = 0; i < 4; i++)
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{
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uint8_t enc_size = (desc->operand_sizes >> 2 * i) & 3;
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instr->operands[i].size = operand_sizes[enc_size];
|
|
}
|
|
|
|
if (DESC_HAS_IMPLICIT(desc))
|
|
{
|
|
FdOp* operand = &instr->operands[DESC_IMPLICIT_IDX(desc)];
|
|
operand->type = FD_OT_REG;
|
|
operand->reg = 0;
|
|
}
|
|
|
|
if (DESC_HAS_MODRM(desc))
|
|
{
|
|
FdOp* operand1 = &instr->operands[DESC_MODRM_IDX(desc)];
|
|
|
|
FdOp* operand2 = NULL;
|
|
if (DESC_HAS_MODREG(desc))
|
|
{
|
|
operand2 = &instr->operands[DESC_MODREG_IDX(desc)];
|
|
}
|
|
retval = decode_modrm(buffer + off, len - off, mode, instr, prefixes,
|
|
operand1, operand2);
|
|
|
|
if (UNLIKELY(retval < 0))
|
|
{
|
|
return -1;
|
|
}
|
|
|
|
off += retval;
|
|
}
|
|
else if (DESC_HAS_MODREG(desc))
|
|
{
|
|
// If there is no ModRM, but a Mod-Reg, its opcode-encoded.
|
|
FdOp* operand = &instr->operands[DESC_MODREG_IDX(desc)];
|
|
uint8_t reg_idx = buffer[off - 1] & 7;
|
|
#if defined(ARCH_X86_64)
|
|
reg_idx += prefixes & PREFIX_REXB ? 8 : 0;
|
|
#endif
|
|
operand->type = FD_OT_REG;
|
|
operand->reg = reg_idx;
|
|
}
|
|
|
|
if (UNLIKELY(DESC_HAS_VEXREG(desc)))
|
|
{
|
|
FdOp* operand = &instr->operands[DESC_VEXREG_IDX(desc)];
|
|
operand->type = FD_OT_REG;
|
|
operand->reg = vex_operand;
|
|
}
|
|
|
|
uint32_t imm_control = DESC_IMM_CONTROL(desc);
|
|
if (imm_control == 1)
|
|
{
|
|
FdOp* operand = &instr->operands[DESC_IMM_IDX(desc)];
|
|
operand->type = FD_OT_IMM;
|
|
operand->size = 1;
|
|
instr->imm = 1;
|
|
}
|
|
else if (imm_control == 2)
|
|
{
|
|
FdOp* operand = &instr->operands[DESC_IMM_IDX(desc)];
|
|
operand->type = FD_OT_MEM;
|
|
operand->reg = FD_REG_NONE;
|
|
operand->size = op_size;
|
|
instr->idx_reg = FD_REG_NONE;
|
|
|
|
if (UNLIKELY(off + addr_size > len))
|
|
return -1;
|
|
#if defined(ARCH_386)
|
|
if (addr_size == 2)
|
|
instr->disp = LOAD_LE_2(&buffer[off]);
|
|
#endif
|
|
if (addr_size == 4)
|
|
instr->disp = LOAD_LE_4(&buffer[off]);
|
|
#if defined(ARCH_X86_64)
|
|
if (addr_size == 8)
|
|
instr->disp = LOAD_LE_8(&buffer[off]);
|
|
#endif
|
|
off += addr_size;
|
|
}
|
|
else if (imm_control != 0)
|
|
{
|
|
FdOp* operand = &instr->operands[DESC_IMM_IDX(desc)];
|
|
|
|
uint8_t imm_size;
|
|
if (DESC_IMM_BYTE(desc))
|
|
{
|
|
imm_size = 1;
|
|
}
|
|
else if (UNLIKELY(instr->type == FDI_RET_IMM))
|
|
{
|
|
imm_size = 2;
|
|
}
|
|
else if (UNLIKELY(instr->type == FDI_ENTER))
|
|
{
|
|
imm_size = 3;
|
|
}
|
|
#if defined(ARCH_X86_64)
|
|
else if (mode == DECODE_64 && UNLIKELY(imm_control == 4))
|
|
{
|
|
// Jumps are always 8 or 32 bit on x86-64.
|
|
imm_size = 4;
|
|
operand->size = 8;
|
|
}
|
|
#endif
|
|
else if (prefixes & PREFIX_OPSZ)
|
|
{
|
|
imm_size = 2;
|
|
}
|
|
#if defined(ARCH_X86_64)
|
|
else if (mode == DECODE_64 && (prefixes & PREFIX_REXW) &&
|
|
instr->type == FDI_MOVABS_IMM)
|
|
{
|
|
imm_size = 8;
|
|
}
|
|
#endif
|
|
else
|
|
{
|
|
imm_size = 4;
|
|
}
|
|
|
|
if (UNLIKELY(off + imm_size > len))
|
|
{
|
|
return -1;
|
|
}
|
|
|
|
if (imm_size == 1)
|
|
{
|
|
instr->imm = (int8_t) LOAD_LE_1(&buffer[off]);
|
|
}
|
|
else if (imm_size == 2)
|
|
{
|
|
instr->imm = (int16_t) LOAD_LE_2(&buffer[off]);
|
|
}
|
|
else if (imm_size == 3)
|
|
{
|
|
instr->imm = LOAD_LE_2(&buffer[off]);
|
|
instr->imm |= LOAD_LE_1(&buffer[off + 2]) << 16;
|
|
}
|
|
else if (imm_size == 4)
|
|
{
|
|
instr->imm = (int32_t) LOAD_LE_4(&buffer[off]);
|
|
}
|
|
#if defined(ARCH_X86_64)
|
|
else if (imm_size == 8)
|
|
{
|
|
instr->imm = (int64_t) LOAD_LE_8(&buffer[off]);
|
|
}
|
|
#endif
|
|
off += imm_size;
|
|
|
|
if (imm_control == 4)
|
|
{
|
|
instr->imm += instr->address + off;
|
|
}
|
|
|
|
if (UNLIKELY(imm_control == 5))
|
|
{
|
|
operand->type = FD_OT_REG;
|
|
operand->reg = (instr->imm & 0xf0) >> 4;
|
|
}
|
|
else
|
|
{
|
|
operand->type = FD_OT_IMM;
|
|
}
|
|
}
|
|
|
|
if ((prefixes & PREFIX_LOCK) && !desc->lock)
|
|
return -1;
|
|
if ((prefixes & PREFIX_LOCK) && instr->operands[0].type != FD_OT_MEM)
|
|
return -1;
|
|
|
|
instr->size = off;
|
|
|
|
return off;
|
|
}
|