Alexis Engelke
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e63fa88da4
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Minor fixes (RETF, POPCNT, +PDEP, +PEXT)
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2020-02-10 17:17:39 +01:00 |
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Alexis Engelke
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19b76c809e
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Add MMX and several other instructions
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2019-11-03 11:56:24 +01:00 |
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Alexis Engelke
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c5281e2f58
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Add support for several small ISA extensions
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2019-11-02 22:17:43 +01:00 |
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Alexis Engelke
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7e89bee1f0
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Further memory operand annotations
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2019-11-02 22:17:20 +01:00 |
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Alexis Engelke
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df4e2725d4
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Annotate several more memory-only instructions
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2019-11-02 21:50:02 +01:00 |
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Alexis Engelke
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92e104d411
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Finally fix moves from/to CR/DR registers
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2019-11-02 21:48:36 +01:00 |
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Alexis Engelke
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bd6c7ceebe
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Begin enforcing memory operand requirements
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2019-11-02 19:21:29 +01:00 |
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Alexis Engelke
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32d65fbf19
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Fix CR/DR move operand sizes
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2019-11-02 19:20:47 +01:00 |
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Alexis Engelke
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194a7d6831
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Add REP-prefix table
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2019-11-02 19:01:23 +01:00 |
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Alexis Engelke
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21cea7ff23
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Fix GETSEC prefix encoding
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2019-11-02 19:00:11 +01:00 |
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Alexis Engelke
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5ba2859c7b
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Fix ADDSUBPS encoding
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2019-11-02 17:53:21 +01:00 |
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Alexis Engelke
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194b99065e
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Add RSM instruction
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2019-11-02 17:32:51 +01:00 |
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Alexis Engelke
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d728f8f4af
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Fix UD0 encoding
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2019-11-02 17:10:22 +01:00 |
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Alexis Engelke
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8efc33ca4d
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Add LSS/LFS/LGS instructions
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2019-11-02 17:10:04 +01:00 |
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Alexis Engelke
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8c51339c49
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Add moves from/to control/debug registers
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2019-11-02 17:09:41 +01:00 |
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Alexis Engelke
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9d6e357d54
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Add INT1
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2019-11-02 17:09:22 +01:00 |
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Alexis Engelke
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915c2296c1
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Add support for far returns
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2019-11-02 17:08:37 +01:00 |
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Alexis Engelke
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07709fcdd8
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Fix operand ordering of MOV[LH]P[S]
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2019-05-06 08:10:50 +02:00 |
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Alexis Engelke
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24b79f71b6
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Add missing FPU instructions
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2019-05-05 12:53:29 +02:00 |
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Alexis Engelke
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dff78c5a86
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Support VSIB encoding
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2019-04-27 11:16:09 +02:00 |
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Alexis Engelke
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1b474a04ac
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Add support for missing AVX instructions
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2019-04-27 11:10:22 +02:00 |
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Alexis Engelke
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14c5590413
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Set size of rare memory operands to zero
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2019-02-24 17:11:32 +01:00 |
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Alexis Engelke
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2dd1c99a81
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Fix operand size of some SSE instructions
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2019-02-24 15:46:09 +01:00 |
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Alexis Engelke
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d5d0009070
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Distinguish VZEROALL and VZEROUPPER
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2019-02-24 15:45:37 +01:00 |
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Alexis Engelke
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dfd70eef39
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Fix bug with VMOV[DQ] operand width in 32-bit mode
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2019-02-24 10:09:18 +01:00 |
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Alexis Engelke
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b2b29239b1
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Disallow LOCK prefix for non-lockable instructions
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2019-02-24 09:26:23 +01:00 |
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Alexis Engelke
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1670a52047
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Fix decoding of CVTTS[SD]2SI
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2019-02-23 16:33:32 +01:00 |
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Alexis Engelke
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81224d1748
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Fix some FPU instruction operand sizes
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2019-02-10 16:17:33 +01:00 |
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Alexis Engelke
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b328067e60
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Minor update of instruction definitions
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2019-02-10 10:49:22 +01:00 |
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Alexis Engelke
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617ebe5c8a
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Decode additional CET instructions
Mainly motivated to decode binaries compiled by recent GCC versions,
which now include CET instructions like endbr64 all over the place.
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2018-12-31 13:25:15 +01:00 |
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Alexis Engelke
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a3f77dbf49
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Initial commit
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2018-04-08 13:45:13 +00:00 |
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