Commit Graph

5 Commits

Author SHA1 Message Date
Alexis Engelke
dc286b14f2 Unify instruction mnemonics [API break]
It is a longer standing issue that some instructions like ADD, IMUL, and
SHL have multiple mnemonics for different encoding forms. This is a
relict from a time where such information was not stored in the
instruction decoding. This, however, is no longer the case and therefore
the extra mnemonics just increase the number of cases to be handled by
users.
2020-02-20 10:56:17 +01:00
Alexis Engelke
f6a66ea4fb Use special root table for VEX
Some instruction opcodes have an entirely different encoding when a VEX
prefix is present. For example, 0f41 is CMOVNO without mandatory
prefixes while VEX.NP.W0.L1.0f41 is KANDW with a mandatory prefix. To
avoid collisions, the VEX prefix is better handled as a completely
separate decode tree, at the cost of a slight increase in table size.
2020-02-10 20:34:37 +01:00
Alexis Engelke
dfd70eef39 Fix bug with VMOV[DQ] operand width in 32-bit mode 2019-02-24 10:09:18 +01:00
Alexis Engelke
8fdfe53822 Output more available information in formatter
The formatter now includes the following information:

- Segment overrides
- Address-size overrides
- REP/REPNZ prefixes
- LOCK prefix
- High-byte registers (determined using presence of REX prefix)
2019-01-13 20:38:15 +01:00
Alexis Engelke
a3f77dbf49 Initial commit 2018-04-08 13:45:13 +00:00