Commit Graph

345 Commits

Author SHA1 Message Date
Alexis Engelke
29a62bd1c9 instrs: Add WRMSRNS 2022-11-27 13:39:37 +01:00
Alexis Engelke
769218bbc9 instrs: Add RDMSRLIST/WRMSRLIST 2022-11-27 13:39:37 +01:00
Alexis Engelke
99bea8a81e instrs: Fix VPERMQ and VPERMPD encoding 2022-11-27 13:39:37 +01:00
Alexis Engelke
7142478f41 encode: Fix MVR operand order 2022-11-27 13:39:37 +01:00
Alexis Engelke
d150ccf1a5 instrs: Fix VMI encoding operands and add tests 2022-11-27 13:39:37 +01:00
Alexis Engelke
0e0b03f839 format: Drop fd_strplcpy 2022-11-25 14:58:58 +01:00
Alexis Engelke
6facb5f08c format: Use logarithmic address/operand sizes
This simplifies register and pointer size formatting.
2022-11-25 14:50:16 +01:00
Alexis Engelke
1a4eb124a7 fadec: Expose logarithmic sizes 2022-11-25 14:47:58 +01:00
Alexis Engelke
180cc059ed instrs: Fix INVEPT/INVVPID memory operand size 2022-11-25 14:34:57 +01:00
Alexis Engelke
b817713ae8 decode: Store operand size logarithmic 2022-11-25 14:34:22 +01:00
Alexis Engelke
1291603246 decode-test: Add cases for far jmp/ret 2022-11-25 12:38:52 +01:00
Alexis Engelke
1c04ded9b7 decode: Merge zeroreg and vexreg
There is no instruction that uses an implicit register and an
VEX-encoded register at the same time. Thus, we can merge vexreg and
zeroreg in the instruction descriptor; the zeroreg value will be added
to the vex-operand (which is zero unless set by a VEX prefix).

This also frees 4 descriptor bits for use with AVX-512 (which will
probably need 1-2 additional unused bits, probably from the type).
2022-11-20 15:25:37 +01:00
Alexis Engelke
19b9d82630 instrs: Add VAES instructions 2022-11-07 08:58:11 +01:00
Alexis Engelke
c15600a1d1 decode-test: Add two more MOVSX cases 2022-11-05 13:56:56 +01:00
Alexis Engelke
0c20aa4f19 decode: remove unnecessary shifts 2022-11-05 13:56:27 +01:00
Ole André Vadla Ravnås
a05d52fdd0 windows: Add support for building with MSVC 2022-11-01 19:22:43 +01:00
Ole André Vadla Ravnås
e9d961e316 meson: Simplify run_command()
By moving to the new API in Meson 0.47. This also means we avoid a
deprecation warning.
2022-11-01 19:22:37 +01:00
Ole André Vadla Ravnås
ffb40fb51f meson: Require Meson >= 0.49
Needed for compiler.get_argument_syntax().
2022-11-01 19:22:31 +01:00
Alexis Engelke
1f0ef1ba0c parseinstr: Remove duplicate encode mnem generator 2022-02-26 10:11:12 +01:00
Alexis Engelke
6b8c2968c1 encode2: Add new encoder API, one func per instr.
This is an *experimental* (read: unstable) API which exposes encoding
functionality as one function per instruction. This makes the encoding
process itself significantly faster, at the cost of a much larger binary
size (~1 MiB of code, no data) and much higher compilation time.
2022-02-20 17:21:04 +01:00
Alexis Engelke
003c7ca750 encode-test: Make cases generally usable
This is a preparation for a new API which exposes different instructions
as different functions.
2022-02-20 17:18:15 +01:00
Alexis Engelke
2fd83903cf meson,parseinstrs: Make decode and encode optional 2022-02-20 17:15:21 +01:00
Alexis Engelke
87fe6314b8 instrs: Disambiguate instr type by mnemonic 2022-02-20 15:38:12 +01:00
Alexis Engelke
e78a89b610 instrs: Annotate 67h and segment override usage
Some instructions honor an address-size override or a segment override,
even in the absence of a directly encoded memory operand.

These annotations are not yet used, but may be used in future to
optimize the size of encoded instructions.
2022-01-06 10:31:09 +01:00
Alexis Engelke
5e546f5458 instrs: Fix INTO flags 2022-01-06 10:29:02 +01:00
Alexis Engelke
f9a773c619 format: Fix unused parameter warning 2022-01-06 09:56:01 +01:00
Alexis Engelke
38a7a5f075 format: Fix cast alignment warning for __m128i 2022-01-06 09:55:29 +01:00
Ole André Vadla Ravnås
e98e96c28c decode: Remove inline hint on table_walk()
To avoid GCC warnings when building with `-Os`:

    warning: inlining failed in call to 'table_walk': call is
        unlikely and code size would grow [-Winline]

I don't know if this causes a performance regression when optimizing for
speed instead of size, but perhaps there's a different way we can help
the compiler make this decision in such cases.
2022-01-06 09:54:47 +01:00
Ole André Vadla Ravnås
8e56088c6f encode: Fix OPC_*_MSK on 32-bit systems
Where we'd end up losing the upper bits.

GCC catches this and emits a warning such as:

    warning: result of '7 << 31' requires 35 bits to represent, but
        'long int' only has 32 bits [-Wshift-overflow=]
2022-01-06 09:46:50 +01:00
Ole André Vadla Ravnås
5c35f0e40e decode: Fix LOAD_LE_8() on 32-bit systems
Where size_t is only 32 bits wide, and we end up losing the upper bits.

GCC catches this and emits a warning such as:

    warning: left shift count >= width of type [-Wshift-count-overflow]
2022-01-06 09:45:21 +01:00
Ole André Vadla Ravnås
4b42ddb567 meson: Override provided dependency
For convenience when used as a subproject.
2022-01-05 10:06:37 +01:00
Alexis Engelke
204580f480 tests: Move to root directory 2021-09-22 13:16:58 +02:00
Alexis Engelke
16c5c64932 tests: Add more corner cases 2021-09-22 12:15:59 +02:00
Alexis Engelke
1bd5f7c572 decode: Set address size when decoding prefixes 2021-09-20 13:52:06 +02:00
Alexis Engelke
a150822fe1 meson: Add -fstrict-aliasing if supported 2021-09-19 17:06:59 +02:00
Alexis Engelke
49984c940c parseinstrs: Encode struct in InstrDesc 2021-09-14 18:15:38 +02:00
Alexis Engelke
c8ff70d436 tests/decode: Test more instructions and operands 2021-09-13 17:44:34 +02:00
Alexis Engelke
4193ef96bf parseinstrs: Generate more statistics 2021-09-13 17:44:00 +02:00
Alexis Engelke
e5cdc57743 parseinstrs: Minor simplification 2021-09-13 17:43:12 +02:00
Alexis Engelke
bf0425f057 decode: Expose immediate in RVMR encodings
The AMD64 instructions VPERMIL2PS and VPERMIL2PD (currently not
supported) encode a fifth immediate operand in the lower bits of the
re-purposed immediate. Expose this value in any case so that no
information gets lost during decoding.
2021-09-13 17:38:24 +02:00
Alexis Engelke
7229f13742 parseinstrs: Don't generate 16-bit version for I66 2021-09-13 17:28:49 +02:00
Alexis Engelke
effc0c7e49 parseinstrs: Fold trie layers with only one child 2021-09-13 17:27:47 +02:00
Alexis Engelke
71c0daf581 instrs: Change operand format
This changes the instruction description format:

- Use Intel/AMD terminology for describing operands (where applicable)
- Group instructions by ISA extension
- Indicate read/written status flags
2021-09-13 17:26:43 +02:00
Alexis Engelke
e41d6c26f8 parseinstrs: Make superstring function generic 2021-09-11 13:19:17 +02:00
Alexis Engelke
1fcacdeda7 parseinstrs: Optimize mnemonic compression
As the formatter no longer demands a null-terminated string, mnemonics
can arbitarily overlap and therefore save space.

This is the shortest superstring problem, which is NP-hard. This is
currently approximated with a greedy heuristic.
2021-09-11 13:05:34 +02:00
Alexis Engelke
e164803037 instrs: Support FRED instructions 2021-06-13 16:01:03 +02:00
Alexis Engelke
7df4c9542f format: Reduce size of register name table 2021-06-13 15:59:44 +02:00
Alexis Engelke
99a1fbeee1 format: Major refactoring for performance 2021-05-30 14:25:38 +02:00
Alexis Engelke
50f052488d decode: More precise register types 2021-04-02 17:20:23 +02:00
Alexis Engelke
d67eb93148 general: Improve documentation 2021-04-02 11:31:28 +02:00